Can I use the Done signal in FPGA to reset my design

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Thank God ! Finally I caaaaaaaaaaatch it :lol:

It works with the UCF constrain : INST "signal name" INIT = value;

The problem was that my code is FSM based
so I defined the current state and next state flip flops with zeros as my initia ( reset ) state is defined as zero in the code !

But when I refered to the synthesizer report I found a statment :
( The FSM was implemented as one-hot )
In one hot ; for example If you have five states ; It creats 5 f/fs
and the coding is
00001
00010
00100
01000
10000
so , there is no "00000" state and all my tries was to initialize with zeros !

That's all ; I just want to share this with you and also want to thank you all for your posts ...Viva elektroda
 

it is possiple, but I donot recommend this, I always only use DONE as a status signal, DONE has to be pullled up by 330 Ohm resister to vcc if use vritex part. donot screw this signal.
 

If you are using a Xilinx device you can just add the following to your RTL where you declare the flops you are trying to set to a specific INIT value. For example in verilog:

reg [3:0] your_flop /* synthesis xc_props = "INIT=C" */ ;

your_flop should be initialized to 'hC after configuration.

thedog
 

I don't meet this question when i was using the chip.
but i think you can use reset circuit with long reset time. and I think the programing of the FPGA should not take so much time. if really, you can make use of parallel programing, which can save your programming time. try it.
 

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