Can I use emacs to compile Verilog or SystemVerilog design?

[Renjie]

Hi guys,

I've been learning emacs these days. Does anyone knows how to compile the design in emacs? Do I need to install any plugins?

Thank you so much!

 

[john blue]

Hi,


You can make Emacs start your simulator by putting this in .emacs (assuming you're using
verilog-mode):

(add-hook 'verilog-mode-hook
(lambda ()
(make-local-variable 'compile-command)
(setq compile-command "./trun --vcs +SST")))

Then I have
(global-set-key [f9] 'compile)

Whenever I hit F9 it will run the compile command. If I'm working on C
code that will be make. If I'm using verilog mode that will be "./trun --vcs +SST", e.g. a script to run my testbench and generate a signalscan dump file.

 

[BlackHelicopter]

Could someone explain how to do this with Modelsim? Will it highlight compiler errors and warnings as well?

I guess I don't quite understand what the post above is doing.