Can I use a pulse like following in VHDL?

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EDA_hg81

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Can I use a pulse like following:

CLK is the global Clock signal

Code: 
Process (CLK) 

A <= B and C;

End;

Process ( A )

If ( A’event and A= ‘1’)

More Code here

End ;
So many thanks for your suggestions.
 

Process (CLK)

A <= B and C;

End;

B and C also need in sensitivity list


Process ( A )

If ( A’event and A= ‘1’)

More Code here

End ;

it is ok no problem
 

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    EDA_hg81

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Should I connect A with a buffer inside XilinX FPGA?

Thanks.

Added after 4 minutes:

In my mind, I want to use Pulse A to trigger a part of code.

Pulse A is not a free run clock.

What I am worry about is the fan-out ability of pulse A inside Xilinx FPGA.

Thanks.
 

If your A signal is bigger than a clock cycle, it's really better that you reveal it's rising edge synchronously (yes you'll have 2 clk of delay, but usually it's not a problem) and use this generated sygnal as an enable in your synchronous design.

Done that, you'll have that your code will be fully synchronous and that's a lot better solution.
You'll have also no fan out problem.
 

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    EDA_hg81

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My idea is want to capture the transient time of Pulse A.

and Pulse A may be only one clock width.

How about the codes as following:

Code: 
A <= B and C;

Process ( risingedge (A) )

More code here

End process.

Thanks.
 

A’event and A= ‘1’ and rising_edge(A)are exact synonyms, anything said regarding the first also appies to the latter.

It's not generally prohibited, to use any signal, also from prior logical pcrocessing, as an edge sensitive clock. And it's particularly not a problem of fan-out. But the asynchronous nature of the design may imply some problems, depending onf the character of the more code here. A usual way to avoid them from the start is to use a synchronous edge detection instead of clocking a process with an unrelated clock. For a short signal, direct clocking may be the only option. But then, all input and output signals to the process have to be treated with caution, cause violation of setup and hold timing may result in unexpected logical behaviour.
 

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    EDA_hg81

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