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For instance, if this ESD diode consists of a N+NWELL to Psubstrate diode then stacking is not possible. The upper diode will go into avalanche breakdown at about 10V as before. The upper diode in the stack must be a so-called 'floating diode' type, which means that both terminals (Anode/Cathode) can be biased separately from the supply lines (Vss/vdd).
For instance P+/Nwell diodes in a P-substrate technology can be stacked.
Can you share more information about the application?
- Sensitive circuit to be protected?
- ESD requirements?
- Process node / foundry?
- Leakage specification?
- Maximum area?
The problem with zener-based ESD protection is the rather large area required. Think about a diode of 2000um-5000um perimeter to protect against 2kV HBM. In you example you will need two of these diodes in series.
Also the parasitic capacitance will be quite large... about 10 pF just for the junction alone. if your input signal has a bandwidth above 500MHz this can be a problem.
The diode stack is also quite resistive under ESD stress. Do you have an idea of the failure voltage of the IO circuit connected to the 16V pad? Can it tolerate 20-30V during 1us (ESD timeframe)?
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