[SOLVED] Can i pass mutiple interface to a module ??

module dut_top#(
                 parameter WB_ADDR_WIDTH = 16,
                 parameter WB_DATA_WIDTH = 32,
                 parameter SOC_BASE_ADDRESS = 'h0F00,
                 parameter MAX_BOUNDRY = 'h1000
              )
              ( input clock , resetn,  ahb_intf ahb_if0, ahb_if1, ahb_if2, ahb_if3);

/*
// Wishbone interface: Output from AHB2WB bridge
  wb_intf wb_if();
// Output from interconnect and input to AHB2WB bridge
  ahb_intf ahb_if4(clock, resetn);
// Bus Interface connected with the IP
  bus_intf  bus_if0();
  bus_intf  bus_if1();
  bus_intf  bus_if2();
  bus_intf  bus_if3();

// Connect all output from master to the input of arbiter
 ahb_arbiter arbiter(ahb_if0, ahb_if1, ahb_if2, ahb_if3, ahb_if4, clock  , resetn);

// AHB Arbiter output connected to wishbone bridge
  ahb2wb#(.AWIDTH(WB_ADDR_WIDTH),
           .DWIDTH(WB_DATA_WIDTH)
         )
          BRIDGE( .adr_o(wb_if.wb_addr_i),
                  .dat_o(wb_if.wb_dat_i),
                  .dat_i(wb_if.wb_dat_o),
                  .ack_i(wb_if.wb_ack_o),
                  .cyc_o(wb_if.wb_cyc_i),
                	.we_o(wb_if.wb_we_i),
                  .stb_o(wb_if.wb_stb_i),
                  .hclk(clock),
                  .hresetn(resetn),
                  .haddr(ahb_if4.HADDR),
                  .htrans(ahb_if4.HTRANS),
                  .hwrite(ahb_if4.HWRITE),
                  .hsize(ahb_if4.HSIZE),
                  .hburst(ahb_if4.HBURST),
                  .hsel(1'b1),             // Since one slave.. hsel is always 1.
                  .hwdata(ahb_if4.HWDATA),
                  .hrdata(ahb_if4.HRDATA),
                  .hresp(ahb_if4.HRESP),
                  .hready(ahb_if4.HREADY),
                  .clk_i(wb_if.clock),
                  .rst_i(wb_if.arst)
                );

// Connect output of bridge to the input of decoder
 wb_decoder  #(.SOC_BASE_ADDRESS(SOC_BASE_ADDRESS),
                      .MAX_BOUNDRY(MAX_BOUNDRY)
                     ) decoder
                     (wb_if, bus_if0, bus_if1, bus_if2, bus_if3);

 ip_top ( bus_if0, spi_if,  clock, resetn);

*/
endmodule