Can i mix VHDL and verilog in my design?

[cafukarfoo]

mix vhdl and verilog

Hello everyone,

Let say i have a IP block written in VHDL.

I would like to use this IP block and interface through verilog.

Is that possible? A quick example will be very helpful.

Thanks.

 

[gck]

verilog vhdl mix

Its possible to do the mix design. I belive you are using Modelsim for simulation purpose.

Just go through the help doc called " Mixed simulation" You will get the idea about how to interface and other.

 

[tut]

mixing verilog with vhdl

yes it is possible, if your simulator supports (most of them generally do :| )

An Example:

say u have a VHDL IP:

entity test is
port (
  a: in std_logic;
  b: in std_logic;
  c: out std_logic
);
end test;

u'll instantiate this in verilog code as:

test i_test(
  .a(),
  .b(),
  .c()
);

 

[sree205]

instantiate verilog ip in vhdl

sometimes the top module of individual VHDL blocks are written using verilog, because i believe its simpler to instantiate it in verilog than in vhdl, where component instantiation along with port map has to be done separately.

Also, i'm not so sure about hierarchical access to internal registers(which verilog supports) will be possible in VHDL. i'd love to proven wrong on this one.

Btw, for the example posted above, if i try to compile using modelsim (vlog) , i get a compile error because libraries are not part of verilog. How to overcome this situation?

 

[FvM]

instantiate vhdl block in verilog

Btw, for the example posted above, if i try to compile using modelsim (vlog) , i get a compile error because libraries are not part of verilog. How to overcome this situation?

I don't see, which library you're missing here. It's a nonsense example anyway, cause the instantiated module is connected to nothing, which is identical to omitting it completely.

 

[sree205]

modelsim vhdl with verilog entity

forget the above example. In vhdl code, we use these following two lines (well, atleast these two).

library ieee;
use ieee.std_logic_1164.all;

Now, when a vhdl code is instantiated in a verilog file with these two lines in it, i get an error in modelsim. thats what i meant

 

[FvM]

vhdl mix with block

Libraries have to be setup with ModelSim simulation, generally. But they actually are part of ModelSim, there should be particular ieee directories in your ModelSim installation.

 

[sree205]

mix c and verilog

here is an example code of verilog and VHDL.

library ieee;
use ieee.std_logic_1164.all;

entity OR_ent is
port( x: in std_logic;
y: in std_logic;
F: out std_logic
);
end OR_ent;

architecture OR_beh of OR_ent is
begin
F <= x or y;
end OR_beh;

================================

`include "new.vhd"

module tb_new()

reg x,y;
wire F;

OR_ent or1(.x(x),.y,.F(F));

initial
begin
x=1;
y=1;
#10 x=0;
y=1;
end

endmodule

When i compile the VHDL file with vcom, it compiles fine, when i compile the verilog file with vlog, i get this error.

** Error: new.vhd(2): near ";": syntax error, unexpected ';', expecting "STRING_LITERAL"

Can you tell me where i'm going wrong ?

 

[omara007]

mixed verilog vhdl design

One good reason for using Verilog Top-Levels is that you can then use PLI's.

 

[boardlanguage]

modelsim instantiation verilog in vhdl

One good reason for using Verilog Top-Levels is that you can then use PLI's.

But don't some simulators have restrictions on PLI/VHPI interfacing with mixed-language designs?

 

[FvM]

determine if top module is verilog or vhdl

This of course can't work in a Verilog file:

`include "new.vhd"

You have to compile both sources separately, no include is required. Having the vhdl file imported to your project is enough for ModelSim to know the component definition.