Can I make PA in TSMC 0.18 cmos?

[dd2001]

tsmc 0.18um cmos 3.3v

Can I make PA in TSMC 0.18 cmos? or I have to use a diffrent process? Like SiGe bicmos?

 

[Puppet1]

depends on the application ?

 

[CDRCDR]

It is better to use SiGe BiCMOS

 

[Puppet1]

read this

 

[Colbhaidh]

There are several applications running in TSMC, Chertered etc at 0.18um and 0.13um using PA's. But it does depend on the application.

 

[hrkhari]

It highly dependant on your application and modulation scheme used, for application such as QPSK and QAM modulation PA class A is wise to be used due to its envelope variation characteristic, hence voltage headroom limitation exist in 0.18um technology, in such a situation it is wise to use PA Class E but requires a linear input.

There are also several linearization techniques could be adpted in order to realize PA for nonlinear input.

Rgds

 

[minaflying]

what about the deffrence bettwen the 0.18um and the 0.25um cmos processes when tape out the same sch ,except the chip area.

 

[Colbhaidh]

Sorry - should have qualified the statement before.
For 0.18um and 0.13um - these processes are dual gate. This means there are 1.8V cores and 3.3V IOs. The 3.3V thick gate transistors are the one almost always used for analogue and RF (with several exceptions, but generally). So there is no real gain in area for say a 3.3V PA on 0.18um and 0.25um since the analogue transistors are drawn to a minimum design rule of 0.32um (Chartered) or 0.35um (TSMC).
However, although the sizings may be comparable, the Spice models may be different as the 0.18 & 0.13um processes will have been developed completely independently of the 025 or 0.35um processes.

 

[yearn]

Hi, Colbhaidh, it is said that the Chartered 0.18um 1.8V/3.3V RFCMOS process has no large-signal model. Someone also said this process has not been carried power verification. So it is impossible to design and implement a power amplifier, although such PA require relatively low output power, in this process. Is it true?
I am confused about that, can you give me some comments? Thank you.

 

[LaughingMAN]

Hi,

The main problem you will face in designing PA in cmos is the low quality of the inductors compared to the ones offered in SiGe. On the other hand, if you are planning to use external matching component than this wouldn't be a problem.