Can I ignore these VHDL synthesize warnings?

[gnudaemon]

xst 1304 in vhdl

I have the following code for shifting several bits of a std_logic_vector signal at 1 clock cycle.
When I synthesized it (with Synplify), it outputs some warning about some parts of inputs are not used, and part of outputs are always '0' (the upper part).
I just wonder whether those warnings are ignorable, and those won't cause any problem when porting into real board????
Pls give me opinion if you've experienced it. Thanks a lot
@gnudaemon

--------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity RgtSftMBits4 is
port( reset: in std_logic;
clk: in bit;
input: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0)
);
end RgtSftMBits4;

architecture RgtSftMBits4_bhv of RgtSftMBits4 is
constant deltaM: integer := 3;
constant vectorSize: integer := 7;
begin
process(reset, clk)
begin
if (reset = '1') then
output <= (others => '0');
elsif (clk='1' and clk'event) then
for i in vectorSize downto 0 loop
if (i > vectorSize - deltaM) then
output(i) <= '0';
else
output(i) <= input(i + deltaM);
end if;
end loop;
end if;
end process;
end RgtSftMBits4_bhv;

Added after 39 seconds:

The warnings are as follows

@W: CL111 :"P:\VHDLDocument\VHDLAnalysisAndModelingOfDigitalSystems\FirstPart\rgtSftMbits4.vhd":24:2:24:3|All reachable assignments to output(5) assign '0', register removed by optimization
@W: CL111 :"P:\VHDLDocument\VHDLAnalysisAndModelingOfDigitalSystems\FirstPart\rgtSftMbits4.vhd":24:2:24:3|All reachable assignments to output(6) assign '0', register removed by optimization
@W: CL111 :"P:\VHDLDocument\VHDLAnalysisAndModelingOfDigitalSystems\FirstPart\rgtSftMbits4.vhd":24:2:24:3|All reachable assignments to output(7) assign '0', register removed by optimization
@W:"P:\VHDLDocument\VHDLAnalysisAndModelingOfDigitalSystems\FirstPart\rgtSftMbits4.vhd":24:2:24:3|All reachable assignments to bit 5 of output(7 downto 0) assign 0, register removed by optimization
@W:"P:\VHDLDocument\VHDLAnalysisAndModelingOfDigitalSystems\FirstPart\rgtSftMbits4.vhd":24:2:24:3|All reachable assignments to bit 6 of output(7 downto 0) assign 0, register removed by optimization
@W:"P:\VHDLDocument\VHDLAnalysisAndModelingOfDigitalSystems\FirstPart\rgtSftMbits4.vhd":24:2:24:3|All reachable assignments to bit 7 of output(7 downto 0) assign 0, register removed by optimization
@W:"P:\VHDLDocument\VHDLAnalysisAndModelingOfDigitalSystems\FirstPart\rgtSftMbits4.vhd":13:3:13:7|Input port bit <2> of input(7 downto 0) is unused
@W:"P:\VHDLDocument\VHDLAnalysisAndModelingOfDigitalSystems\FirstPart\rgtSftMbits4.vhd":13:3:13:7|Input port bit <1> of input(7 downto 0) is unused
@W:"P:\VHDLDocument\VHDLAnalysisAndModelingOfDigitalSystems\FirstPart\rgtSftMbits4.vhd":13:3:13:7|Input port bit <0> of input(7 downto 0) is unused

 

[yego]

Re: VHDL synthesize warnings

Apparently, with the numbers declared as constants you'll get on your outputs exactly what the warnings state . The only usable signal will be present on the output lines 4 and 3. The rest will be either reduced to 0 or never used. That is due to the structure of your program and/or constant values. In this case they work together to produce your output. It will influence your design for sure.
IMHO the code should be rewritten and the Warnings can't be ignored unless you know what you're doing.
VHDL is just like C : It does exactly what it is told to do, instead of what the programmer wants it to do.

Regards, yego

 

[arunragavan]

Re: VHDL synthesize warnings

am not gettin any warnins durin synthesis.. is this design ok?

check it up..

with regards,

 

[revolt]

Re: VHDL synthesize warnings

I got the same result as arunragavan with ISE but with same warnings:

====================================================
* HDL Analysis *
=====================================================
Analyzing Entity <rgtsftmbits4> (Architecture <RgtSftMBits4_bhv>).
INFO:Xst:1304 - Contents of register <output<7>> in unit <rgtsftmbits4> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <output<6>> in unit <rgtsftmbits4> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <output<5>> in unit <rgtsftmbits4> never changes during circuit operation. The register is replaced by logic.
Entity <rgtsftmbits4> analyzed. Unit <rgtsftmbits4> generated.


=====================================================
* HDL Synthesis *
=====================================================

Synthesizing Unit <rgtsftmbits4>.
WARNING:Xst:647 - Input <input<2:0>> is never used.
Found 5-bit register for signal <output<4:0>>.
Summary:
inferred 5 D-type flip-flop(s).
Unit <rgtsftmbits4> synthesized.

 

[semiconductorman]

Re: VHDL synthesize warnings

Hi Gnudaemon,
Just look at the for loop you have written ...
/////////////////////////////////////////////////
for i in vectorSize downto 0 loop
if (i > vectorSize - deltaM) then
output(i) <= '0';
else
output(i) <= input(i + deltaM);
end if;
end loop;
////////////////////////////////////////////////////
Considering that reset is not present ... then this is executed ... if we expand this loop u will get
op [7] = '0' ;
op [6] = '0' ;
op [5] = '0' ;
op [4] = ip [7] ;
op [3] = ip [6] ;
op [2] = ip [5] ;
op [1] = ip [4] ;
op [0] = ip [3] ;
/*****************************************;
Now I hope you get the point the tool is making ... op [7 downto 5] are always zero and ip [2 downto 0] are newer used in the logic !!!!! that's y it took the liberty of connecting op [7 downto 5] to ground instead of connecting to any flip flop and it has left ip [2 downto 0] unconnected ..

 

[gnudaemon]

VHDL synthesize warnings

1. Certainly I know there are redundant signals which were not used in my code. Just wonder whether it causes any problem when porting to hardware.
2. The reasoning of such code is sometimes only few upper bits are needed to combine with series of '0' to form a new std_logic_signal.

 

[Ice-Tea]

Re: VHDL synthesize warnings

NO, it will not cause any troubles. Th etool just figures that since the signal is always '0' anyways, there's no need to blow a register on that one.

The only way I can think of how this could cause a different behaviour is if you'd actually count on the design not to meet timings in some way and that the absence of he register'd cause your design to meet timing after all.

 

[gnudaemon]

Re: VHDL synthesize warnings

The only way I can think of how this could cause a different behaviour is if you'd actually count on the design not to meet timings in some way and that the absence of he register'd cause your design to meet timing after all.

What do you mean by 'meet timing here'?
This is of course not a good design. I just want to know that whether some synthesis warnings can be ignored when porting to the real port.
I have tested examples of logical shifters from some books.
They shift only 1 bit at a time, which left one end with bit '0' (similar to my example above). Synthesis also outputs the warning for invariant signal.

 

[canoe]

Re: VHDL synthesize warnings

the program may be good if as following:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity RgtSftMBits4 is
port( reset: in std_logic;
clk: in bit;
input: in unsigned(7 downto 0);
output: out unsigned(7 downto 0)
);
end RgtSftMBits4;

architecture RgtSftMBits4_bhv of RgtSftMBits4 is
constant deltaM: unsigned(2 downto 0) :="011";
constant vectorSize:unsigned(2 downto 0) :="111";
begin
process(reset, clk)
begin
if (reset = '1') then
output <= (others => '0');
elsif (clk='1' and clk'event) then
for i in vectorSize downto 0 loop
if (i > (vectorSize - deltaM)) then
output(i) <= '0';
else
output(i) <= input(i + deltaM);
end if;
end loop;
end if;
end process;
end RgtSftMBits4_bhv;

 

[semiconductorman]

Re: VHDL synthesize warnings

The only way I can think of how this could cause a different behaviour is if you'd actually count on the design not to meet timings in some way and that the absence of he register'd cause your design to meet timing after all.

What do you mean by 'meet timing here'?
This is of course not a good design. I just want to know that whether some synthesis warnings can be ignored when porting to the real port.
I have tested examples of logical shifters from some books.
They shift only 1 bit at a time, which left one end with bit '0' (similar to my example above). Synthesis also outputs the warning for invariant signal.

Ofcourse you can choose to ignore these ... that's why these are called warnings and not errors !!!! Infact when you try to integrate a large module with a lot of reused submodules you invariably end up not connecting a few ports and not using a few inputs they always come ... and u can safely ignore them .. warnings are just an indication of something very obivious , the tool tells you this info just so that you know they exist and you don't end up with surprises at the end

 

[jetset]

Re: VHDL synthesize warnings

Why don't you simply use sll, srl or such operands for shifting?