saikrishna1985
Newbie level 1
Hi members,
We have a System clock running at 120MHz, it has 300pS peak to peak jitter.
I am designing a pipeline ADC and my sampling frequency is 1MHz.
I found that due to aperture uncertanity [jitter] my ADC's performance is limited.
Since my sampling frequency is much slower than my main noisy System clock, can I do some kind of filtering and create a new clean Clock?
what other methods can I use to improve jitter at low frequencies?
We have a System clock running at 120MHz, it has 300pS peak to peak jitter.
I am designing a pipeline ADC and my sampling frequency is 1MHz.
I found that due to aperture uncertanity [jitter] my ADC's performance is limited.
Since my sampling frequency is much slower than my main noisy System clock, can I do some kind of filtering and create a new clean Clock?
what other methods can I use to improve jitter at low frequencies?