can I delay 1.5 time units?

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liletian

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Hi Guys

In verilog, I had the following statement:

'timescale 1n/100p (it means the time unit is 1n with resolution of 100p).

So I can put

#0.1 in the testbench to delay 100p?

how about

#0.01?

Thanks
 

dave_59 said:
Use SystemVerilog for your testbench and write
#0.1ns
Never use unit-less delays in your testbench
Click to expand...
What about those of us who don't have a simulator that supports SystemVerilog?

Maybe you can send me a free perpetual use Questa license so I can use #0.1ns in my testbench! ;-)
 

dave_59 said:
Use SystemVerilog for your testbench and write

#0.1ns

Never use unit-less delays in your testbench
Click to expand...

Those delay is for simulation verification only. It will not be synthesized into the hardware, right?

Thanks

What do you mean never use unit-less delays in testbench? You mean we should never use
#0.1 correct?
 

All versions of ModelSim including free versions (student and Altera editions) all support basic SystemVerilog constructs. Just use a *.sv file extension for files containing SystemVerilog syntax.

Yes, I mean alwayss use #0.1ns instead of #0.1

Synthesis tools ignore all delays in your source code assuming they are just there to approximate actual delays and remove race conditions for simulation verification.
 

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