kvn0smnsn
Junior Member level 2
I've built a module (Equ) and a module (t_Equ) to test it, and put it in the upper two windows of EDA Playground. Module (Equ) uses two modules I've already created, (Mux) and (Nt). Module (Mux) itself uses (Nt). The code for (Equ) is:
and the code for (t_Equ) is:
So when I click on
(Run) the bottom window says:
Code:
// (c) Kevin Simonson 2024
module Equ ( result, left, right);
output result;
input left, right;
wire ntRght;
Nt nt( ntRght, right);
Mux mx( result, left, right, ntRght);
endmodule
Code:
// (c) Kevin Simonson 2024
module t_Equ;
reg lft;
reg rht;
wire rslt;
Equ eq( rslt, lft, rht);
initial
begin
lft = 1'b0;
rht = 1'b0;
#2 rht = 1'b1;
#2 lft = 1'b1;
rht = 1'b0;
#2 rht = 1'b1;
end
always @( rslt, lft, rht)
begin
$display
( "time: %2t, rslt: %1d, lft: %1d, rht: %1d."
, $time , rslt , lft , rht );
end
endmodule
(Run) the bottom window says:
Now I can get this to compile by taking the code for (Nt) and the code for (Mux) and adding it at the beginning of the code in my right window, before the code for (Equ). But that's kind of a bother, and will just get more difficult as I add more modules. Is there a way to tell EDA Playground to look for modules in some set of directories? Or am I stuck just concatenating all the Verilog files my Verilog refers to to the beginning of that Verilog file?Parsing design file 'design.sv'
Parsing design file 'testbench.sv'
Top Level Modules:
t_Equ
TimeScale is 1 ns / 1 ns
Error-[URMI] Unresolved modules
design.sv, 8
"Nt nt(ntRght, right);"
Module definition of above instance is not found in the design.
Error-[URMI] Unresolved modules
design.sv, 9
"Mux mx(result, left, right, ntRght);"
Module definition of above instance is not found in the design.
2 errors
CPU time: .187 seconds to compile
Exit code expected: 0, received: 255
Done