can anyone help me with this error msg?

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aeneas81

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Dear all,
I've tried to compile some code using Altera Quartus II but was unsuccessful because of the following error :

Error: VHDL error at usb_controller.vhd(281): can't infer register for signal tx_mode[1] because signal does not hold its value outside clock edge

I couldn't identify this error as I don't understand what it means, can any one out there help me with this?

Thanks in advance!
 

see whether you have assigned both inside clk edge and outside
otherwise try to assign it to one more net
good luck
 

You assign the signal value into two different processes: the first clocked on the rising edge of the clock and the second clocked on the falling edge (check all the point in wich you change the signal value)
 

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