can anyone help me with this error msg?

[aeneas81]

Dear all,
I've tried to compile some code using Altera Quartus II but was unsuccessful because of the following error :

Error: VHDL error at usb_controller.vhd(281): can't infer register for signal tx_mode[1] because signal does not hold its value outside clock edge

I couldn't identify this error as I don't understand what it means, can any one out there help me with this?

Thanks in advance!

 

[brmadhukar]

see whether you have assigned both inside clk edge and outside
otherwise try to assign it to one more net
good luck

 

[ashishjindal76]

use d flip flop

ashish

 

[BGA]

You assign the signal value into two different processes: the first clocked on the rising edge of the clock and the second clocked on the falling edge (check all the point in wich you change the signal value)