Can anyone help me out in making edge triggered Clock Adders & Multipliers in VHDL

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ETRX_13

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Can anyone help me out in making edge triggered Clock Adders & Multipliers in VHDL

Can anyone help me out in making edge triggered Clock Adders & Multipliers in VHDL

Hello Everyone,

I am doing a mini project on Perfomance Analysis of Different Adders and Multipliers using XILINX Project Navigator 14.5 to write VHDL Code for the same but in that I am getting some errors. For that matter I have asked some people but they say you cant use VHDL for clocking instead use verilog or state machines. Is it True or not plz justify me bcoz i have No Idea about it.

The problem I am facing is that I cant change to another HDL language, as I have mentioned it in my project title.

So Plz can help me out ???

Thank You,

Sincere Regards,
# ETRX_13
 

Re: Can anyone help me out in making edge triggered Clock Adders & Multipliers in VHD

Well, why not past the errors, or what problems you're having.

Everything you can do with verilog you can do with VHDL for FPGA development. I think you either misunderstood these other people or they dont know what they are talking about. For a start, you can write state machines in VHDL.
 
Re: Can anyone help me out in making edge triggered Clock Adders & Multipliers in VHD

Xilinx provides templates if you are using the ISE editor.

Just look under Edit-Language Templates-VHDL-Synthesis Constructs-Coding Examples

Regards
 
Re: Can anyone help me out in making edge triggered Clock Adders & Multipliers in VHD


Yes, the person to whom I approached said that u'll first hav 2 write that codes in State Machines

- - - Updated - - -

And what about timing/gate delay, power consumption, area consumption
How to find these things are there any tools available in XILINX for the calculation of above parameters
or I have to do that another software. specially for accurate gate delay


Thank You,

Sincere Regards,
# ETRX_13
 

Re: Can anyone help me out in making edge triggered Clock Adders & Multipliers in VHD

ETRX_13 said:
And what about timing/gate delay, power consumption, area consumption
How to find these things are there any tools available in XILINX for the calculation of above parameters
or I have to do that another software. specially for accurate gate delay
Click to expand...

Write your code. Compile it, and Xilinx ISE or Vivado will tell you all these things.
 
Re: Can anyone help me out in making edge triggered Clock Adders & Multipliers in VHD

Though the accuracy of said power consumption won't necessarily be very accurate unless you supply vectors from simulation so the tools know the exact toggle behavior of the registers.

You can also download the xpower spreadsheet from Xilinx that allows you to enter the estimated toggle frequencies of the registers/memory/IO/clocks/etc and the number of each. I've had some success using this tool for preliminary PS design. I normally set the spreadsheet to estimate the worst case power and I have yet to see a design require more current on the supply rails. Of course having good estimations of the number of regsiters/RAMs etc prior to designing said logic will help significantly in the quality of the estimate. Just remember to use 12.5% (default value?) for the toggle rate of FFs in the design. If you know some piece of logic has random data on it you can probably go higher.

Regards
 
Re: Can anyone help me out in making edge triggered Clock Adders & Multipliers in VHD



When I am synthesizing my design the following error appears
"More actuals found than formals in portmap"
 

Re: Can anyone help me out in making edge triggered Clock Adders & Multipliers in VHD

ETRX_13 said:
When I am synthesizing my design the following error appears
"More actuals found than formals in portmap"
Click to expand...

This error comes when you are doing mistake in port mapping.
Just check number of port defined in your instantiated design code and in port mapping. there must be mismatch.
 
Re: Can anyone help me out in making edge triggered Clock Adders & Multipliers in VHD

seeker_123 said:
This error comes when you are doing mistake in port mapping.
Just check number of port defined in your instantiated design code and in port mapping. there must be mismatch.
Click to expand...

this is my VHDL code which consist of error mentioned above
I have also attached the txt file with this message

Plz Help me to sought out the error 

Code VHDL - [expand]
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----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    00:01:13 03/25/2014 
-- Design Name: 
-- Module Name:    Latch_RippleAdder - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
                    
                                        --D Flip Flop
 
entity D_ff is
        port(
         din : in STD_LOGIC;
         clk : in STD_LOGIC;
       reset : in STD_LOGIC;
        dout : out STD_LOGIC
         );
end D_ff;
 
architecture Behavioral of D_ff is
 
begin
dff : process (din,clk,reset) is
        
        begin
        if (reset='1') then
            dout <= '0';
        elsif (falling_edge (clk)) then
            dout <= din;
        end if;
    end process dff;
 
end Behavioral;
 
                            --Ripple Carry Adder
                            
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity Ripple_Carry_Adder is
        
        port( A : in std_logic_vector( 3 downto 0);
                B   : in std_logic_vector( 3 downto 0);
            C_in  : in std_logic;
                
                S : out std_logic_vector( 3 downto 0);
                C_out : out std_logic);
                
end Ripple_Carry_Adder;
 
architecture Behavioral of Ripple_Carry_Adder is
 
begin
 
    process(A, B, C_in)
            variable tempC: std_logic_vector( 4 downto 0 );
            variable P : std_logic_vector( 3 downto 0 );
            variable G : std_logic_vector( 3 downto 0 );
        
        begin
                
                tempC(0) := C_in;
                    for i in 0 to 3 loop
                        P(i):= A(i) xor B(i);
                        G(i):= A(i) and B(i);
                        S(i)<= P(i) xor tempC(i);
                tempC(i+1):= G(i) or (tempC(i) and P(i));
                    end loop;
                C_out <= tempC(4);
    end process;
 
end Behavioral;
 
                    --Main Architecture
                    
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--
--entity Latch_Adder is
--end Latch_Adder;
--
--architecture  Latch_Adder of Latch_Adder is
 
entity Latch_RippleAdder is
 
        port( X     : in std_logic_vector( 3 downto 0);
                Y   : in std_logic_vector( 3 downto 0);
                Cy_in : in std_logic;
                RESET : in std_logic;
                CLK : in std_logic;
                
                Sum    : out std_logic_vector( 3 downto 0);
                Cy_out : out std_logic);
 
end Latch_RippleAdder;
 
architecture Behavioral of Latch_RippleAdder is
 
    component D_ff is
        port( din : in STD_LOGIC;
                 clk : in STD_LOGIC;
              reset : in STD_LOGIC;
 
                dout : out STD_LOGIC);
    end component;
 
    component Ripple_Carry_Adder is
        
        port( A : in std_logic_vector( 3 downto 0);
                B   : in std_logic_vector( 3 downto 0);
                C_in : in std_logic;
                
                S : out std_logic_vector( 3 downto 0);
                C_out : out std_logic);
                
    end component;
 
     signal L: std_logic_vector(8 downto 0);
 
begin
 
            D0: D_ff
                PORT MAP(X(0), CLK, RESET, L(0));
            
            D1: D_ff
                PORT MAP(X(1), CLK, RESET, L(1));
 
            D2: D_ff
                PORT MAP(X(2), CLK, RESET, L(2));
            
            D3: D_ff
                PORT MAP(X(3), CLK, RESET, L(3));
            
            D4: D_ff
                PORT MAP(Y(0), CLK, RESET, L(4));
 
            D5: D_ff
                PORT MAP(Y(1), CLK, RESET, L(5));
 
            D6: D_ff
                PORT MAP(Y(2), CLK, RESET, L(6));   
 
            D7: D_ff
                PORT MAP(Y(3), CLK, RESET, L(7));
            
            D8: D_ff
                PORT MAP(Cy_in, CLK, RESET, L(8));
                
            ADD: Ripple_Carry_Adder 
--              PORT MAP(L(0), L(4), L(1), L(5), L(2), L(6), L(3), L(7), L(8), 
--                          Sum(0),Sum(1), Sum(2), Sum(3), Cy_out);
 
                PORT MAP(L(0), L(1), L(2), L(3), L(4), L(5), L(6), L(7), L(8), 
                            Sum(0),Sum(1), Sum(2), Sum(3), Cy_out);
--      Sum(0) <= S(0);
--      Sum(1) <= S(1);
--      Sum(2) <= S(2);
--      Sum(3) <= S(3);
--      
--      Cy_in <= C_in;
--      Cy_out <= C_out;
 
end Behavioral;

THANK YOU EVERYONE.......

Regards,
ETRX_13
 

Attachments

  • latch_txt.txt
    4.3 KB · Views: 118
Last edited by a moderator:

Re: Can anyone help me out in making edge triggered Clock Adders & Multipliers in VHD

This is a perfect example of why you should always use named association for port mapping.
Snippets of your code.
Code VHDL - [expand]
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component Ripple_Carry_Adder is
port( A : in std_logic_vector( 3 downto 0);
B : in std_logic_vector( 3 downto 0);
C_in : in std_logic;
S : out std_logic_vector( 3 downto 0);
C_out : out std_logic);
end component;
 
signal L: std_logic_vector(8 downto 0);
 
ADD: Ripple_Carry_Adder
PORT MAP(L(0), L(1), L(2), L(3), L(4), L(5), L(6), L(7), L(8), 
Sum(0),Sum(1), Sum(2), Sum(3), Cy_out);


as you wrote the above code the instantiation actually means you hook the Ripple_Carry_Adder up as follows:
Code VHDL - [expand]
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ADD: Ripple_Carry_Adder  PORT MAP (
  A => L(0),
  B => L(1),
  C_in => L(2),
  S => L(3),
  C_out => L(4)
);

which I'm sure is not what you intended and is why the error reports you have to many connections.

what you really want is this (excuse me if you can't concatenate in a port map I'm sure someone else will correct me if I'm wrong, I don't regularly code VHDL often, I normally use Verilog exclusively)
Code VHDL - [expand]
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ADD: Ripple_Carry_Adder  PORT MAP (
  A => (L(0) & L(1) & L(2) & L(3)),  -- if you meant L(0) is the most significant bit of A(3 downto 0), otherwise use L(3 downto 0)
  B => (L(4) & L(5) & L(6) & L(7)),
  C_in => L(8),
  S => (Sum(0) & Sum(1) & Sum(2) & Sum(3)),
  C_out => Cy_out
);


You really need to work on your coding style, naming of signals and ports, otherwise you'll always be making these types of mistakes.

regards

P.S. You could have used generics in the D_ff component to allow bused input/outputs then you wouldn't have to use individual bits for the X and Y buses.
 
Last edited:
Re: Can anyone help me out in making edge triggered Clock Adders & Multipliers in VHD

Sir I have just started using VHDL so don't know much about syntax properly
but I ensure you that i will surely rectify my mistakes and flaws

Can you suggest me some tutorials for I will be really thankful to you

Regards,
#ETRX_13
 

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