Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Can anyone explain why are setup & hold of half cycle ssb are both freq dependent

Status
Not open for further replies.

preethi19

Full Member level 5
Full Member level 5
Joined
Jun 30, 2014
Messages
273
Helped
0
Reputation
0
Reaction score
1
Trophy points
16
Activity points
3,474
In full cycle paths setup is freq dependent while hold is not. But why in half cycle ssb paths setup and hold are both freq dependent?
 

Re: Can anyone explain why are setup & hold of half cycle ssb are both freq dependent

In full cycle paths setup is freq dependent while hold is not. But why in half cycle ssb paths setup and hold are both freq dependent?

Your terminology is confusing. What is a half cycle? Same clocks, different clocks?

Hold is also frequency dependent because no clock is perfect, and the clock uncertainty varies with frequency. Most people don't realize this.
 

Re: Can anyone explain why are setup & hold of half cycle ssb are both freq dependent

In full cycle path with the same clock, hold checks for flop to flop path, are not frequency dependent because hold checks are calculated at the same clock edge for the launching and capturing flop. Whereas, in half cycle path with the same clock, hold checks for flop to flop path are checked from either rising edge to falling edge (or falling edge to rising edge ). Based on the frequency of the clock ( assuming 50% duty cycle) , if frequency changes, hold check timing will change.
 
Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top