Next time use GIF file less than 100K instead of JPG file. Nobody want to loss his valuable points.
First time I thought it is a differential comparator. It should compare voltage difference A-B and C-D. But I was confused by R1C1 and R2C2 frequency compensation. If it is comparator it doesn't need any frequency compensation, because never works with feedback. Another thing: it seems to me it is something wrong with this circuit. Where did you get that? As to me if disconnect gate of M21 from drain of M22 and connect to gate of M11 it looks much better.
To my humble opinion I would not say it is a comparator, but an amplifier. The differential stages convert input voltage A-B and C-D to currents. These are substracted, so we get A-B-C+D. Finally the last stage is a transimpedance amplifier. It converts current back to voltage, with a factor 1k namely. The large cap is there to prevent influence of resistor on biasing.
But it seems to me if gate of M21 is connected to drain of M22 transistor M29 never will be switched off. So I prefer connection like I mentioned above.
the way i see it FOM seems to be right... allthough it also looks to me as an Amplifier... the amplifying stages look clear and the same seems for the noise rejection... well i can't be sure but that's my opinion...
If you have posted the circuit as a quiz here, OK
If not, at least give a breif explanation of where you got it from, or what its supposed to do, as everyone here, isn't in the game of guessing or imagining the designers intentions.
It seems to be a differential difference amplifier, but are you sure this circuit works? It is strange that why differential pair A-B and C-D not symmetric, and also why the current mirror in A-side connected to nothing?
*a-b* provide output and it is provided to *bias c-d* pair's load and thus
biasing, magnitude of output provided by c-d stage.
probably reason for having *buffer stage 1* is not much clear to me but i suppose it is for freq compensation and making pair of load in *c-d circuit* identical.
purpose of *bufferstage 2* is to boost the current signal received from
*c-d stage*
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considering this is circuit part of dac - probaly
(a-b) is less significant bit
(c-b) is more significant bit
and a and c are providing reference ground for the bit b and d.