Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Can anybody tell me what does it mean in verilog ?

Status
Not open for further replies.

narasimha_80

Newbie level 5
Newbie level 5
Joined
Nov 29, 2005
Messages
8
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,368
Hi,

Can anybody tell me what does this * mean inside always in verilog ?

always@(*)
begin

---
---

end


Regards,
Narasimha Naik
 

I never see this syntax "*"
 

it just means any event
 

sunking said:
it just means any event

Hi
I had 2 questions regarding it:

1)This "any event" means any event on the signals used in the always block or any event on the signals used in the complete module ????

2) Is such a coding practice encouraged ?????

Thanx
 

From the Verilog standard IEEE Std 1364-2001:

Code:
9.7.5 Implicit event_expression list

The event_expression list of an event control is a common source of bugs in RTL simulations. Users tend to forget to add some of the nets or variables read in the timing control statement. This is often found when comparing RTL and gate level versions of a design. The implicit event_expression, @*, is a convenient shorthand that eliminates these problems by adding all nets and variables which are read by the statement (which can be a statement group) of a procedural_timing_control_statement to the event_expression.

All net and variable identifiers which appear in the statement will be automatically added to the event expression with these exceptions:

  - Identifiers which only appear in wait or event expressions.
  - Identifiers which only appear as a hierarchical_reg_identifier in
    the reg_lvalue of the left hand side of assignments.

Nets and variables which appear on the right hand side of assignments, in function and task calls, or case and conditional expressions shall all be included by these rules.

Examples:

Example 1

  always @(*) // equivalent to @(a or b or c or d or f)
    y = (a & b) | (c & d) | myfunction(f);

Example 2

  always @* begin // equivalent to @(a or b or c or d or tmp1 or tmp2)
    tmp1 = a & b;
    tmp2 = c & d;
    y = tmp1 | tmp2;
  end

Example 3

  always @* begin // equivalent to @(b)
    @(i) kid = b; // i is not added to @*
  end

Example 4

  always @* begin // equivalent to @(a or b or c or d)
    x = a ^ b;
    @* // equivalent to @(c or d)
      x = c ^ d;
  end
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top