I want to implement 8 bit 2's complement multipliers ( for fractional number multiplication ) in VHDL. Can anybody suggest me some algorithms or send me the VHDL/verilog code ?
Actually I want to implement fractional value (in 2's complement) multipliers in VHDL.ie represeneting fractional value in binary and multiplying. Does Booths algorithms support this fractional value multiplication ? If not, Can you suggest any algorithms for this ? I really need some help.
I'm not sure I understand your question. Multiplication of fractions is exactly the same as integer multiplication, except for the position of the decimal point.
For example, let's assume you already have hardware that multiplies two 8-bit integers to get a 16-bit product:
aaaaaaaa * bbbbbbbb = yyyyyyyyyyyyyyyy
You can use the same hardware to multiply two 8-bit fraction values:
aaa.aaaaa * bbbbbb.bb = yyyyyyyyy.yyyyyyy
However, if you don't yet have an integer multiplier, and for some reason your don't want to use the HDL * operator, than that's a different problem.
narasimha_80
according your example
0.5 = 01 in binary;
Then, 01 * 01 =0001
0001 is not 1
0001=00.01=0.25
you should notify the position of the decimal point.
as for algorithm
there are a lot of algorithms for multiplier implemention
you can seach them in google,
it is easy to find a lot of useful links
as anjali said, booth encode is a good method for area and speed, especially 4-based booth encode.
To determine the location of the output decimal point, you add the number of input fraction bits. Five fraction bits times two fraction bits gives you seven fraction bits.