can anybody explain me what CRC is ?

[bigrice]

explain crc

CRC = clock recovery circuit

I don't how to make it realized.

 

[neerajs]

Are you looking for clock recovery or both clock and data recovery? What kind of data stream you are having as input?

 

[Davis]

Clock recovery circuit will extract clock signal from received data. It is generally used in synchronous communication system. Data does not always have transition on each clock edge so it's not easy to derive clock from the data stream. PLL or SAW is used to do this. The extracted clock is generally used to re-sample the data. We call this clock and data recovery (CDR).

 

[vomit]

CRC is most often the "Cyclic Redundancy Check" code used for detecting (but not correcting) bit errors in transmitted data blocks.

Do a Google search.

If you really want to do CDR, check out the major Xilinx and Altera FPGA's, which have CDR built-in.

Otherwise it depends on the kind of data. Also look at the Opencores.org USB core. It has a kind of CDR by oversampling the signal and using a crystal at nearly the correct frequency. If the packet is short, this will ensure that all bits are reclocked correctly, even without having the ideal recovered clock available.

Also check out Hogge phase detectors in combination with phase locked loops. Again, do a Google search

 

[gauiver]

a little detail is given in wyne tommasi digital communication systems. now it also depends upon how the clock is present in the signal. it might be in the form of pilot carrier. other way is that u encode the data stream such that the output signal varies twice during a sinlgle clock pulse for a single output. in soch cases the recieved signal is exored with a half bit delay

 

[bigrice]

Thanks so much for the above comments!
I felt now that CDR would be a more proper description.

Can I make it in digital design by using HDL? or it should be an analog-solve-only thing?

 

[jyq_analog]

Most all clock recovery circuits employ some form of PLL.u can read some books about PLL.

 

[vomit]

Bigrice, you still didn't explain what kind of signal you have. I think the only way to get a good answer is to explain the problem you want to solve. CDR is too big a field to get a simple answer that covers all the cases.

 

[inverter]

also ,there is a publishing press called CRC,mosting engeering handbook,

 

[brucechenwei]

About TCP/IP ,any documents you can learn it from.
If you have any question ,mail to me...

 

[rozerf]

here is sime info of CRC in usb
hope this would be useful

 

[mukeshk]

CRC = cyclic redundancy check
CDR = Clock Data recovery
the basic concept behind CDR is to reduce power by removing extra clock information from the transmitted data and recover clock at the reciving end from the data only