Can any one Plz give the HDL code for fractional clock divider.I need it very badly.

[CHGK.24]

Hi all,
I newly joined in Verilog Domain.
Can any one please give me the code for "fractional clock divider that can divide the incoming clock by 2.5 and 9/7".
I need it Very badly.

Thanks in Advance.

 

[dftrtl]

Please refer to attached document.

 

[CHGK.24]

Can provide the RTL code and fractional clock divider 9/7 also please

 

[CHGK.24]

Hi all,

I think this code is not an big matter,those who know the verilog coding.
Requesting to all,can any one give me the code for dis and help me out.

Thanks in Advance