Mina Magdy
Member level 3
- Joined
- Jun 19, 2012
- Messages
- 67
- Helped
- 6
- Reputation
- 12
- Reaction score
- 5
- Trophy points
- 1,288
- Location
- Cairo, Egypt
- Activity points
- 1,742
Hi
i have a problem in calling module in verilog that when i call a module that make alot of calculation( module calc) it gives me the o/p delayed a clock
and also another module for ram and module for rom thats also delay one clock so when i take the delayed o/p from the (module calc) and but it in the (module RAM) it put the values at wrong places in the ram.
module calc is consists of a module for lookuptable(module LUT) and another module for adding and subtract floating point(module addsub).
i need a form of module that doesn't delay (what could make a delay in a module to avoid) because my system is consists of alot of modules in side each other.
please help me if you can or if you have any suggestion.
i have a problem in calling module in verilog that when i call a module that make alot of calculation( module calc) it gives me the o/p delayed a clock
and also another module for ram and module for rom thats also delay one clock so when i take the delayed o/p from the (module calc) and but it in the (module RAM) it put the values at wrong places in the ram.
module calc is consists of a module for lookuptable(module LUT) and another module for adding and subtract floating point(module addsub).
i need a form of module that doesn't delay (what could make a delay in a module to avoid) because my system is consists of alot of modules in side each other.
please help me if you can or if you have any suggestion.