Thanks for your replies, they are very helpful.
When I set in the GUI gnd layer: nxwell psub, I get the expected results in a simplified layout experiment! Also the extraction of the pwell connected to vdd (for the pmos varactor) looks fine.
The issue with the NWELL seems to be solved
When I use these settings on my circuit, I still see some CC cap to "0" (i did not specify a gnd node name). I think that parasitic cap from a DNW (biased to vssa) is not recognized yet to the correct node.
I use a triple well process from TSMC. I have a psub ring around my block, connected to the pin "vsub" which is only used for this ring. The DNW is biased to vssa, I have some resistors and nmos in this DNW. So I think I must add an additional layer to the gnd layer list for the DNW. In the ruledeck I found the following below, so I took the dnwc for the DNW. However, it does not solve that issue. Should I used another gnd layer for DNW (biased to vssa) or is the order important? This will probably give the same results as shorting the "0" node to gnd, but I think it is good to setup Calibre correct so that the output netlist is as close to the physical reality as it can be.
psub_under = psub_term OR DNW
dnwc = DNW AND nxwell
psub = BULK NOT NW
nxwell = NW NOT NWDMY