quantized
Member level 2
- Joined
- Jul 6, 2012
- Messages
- 51
- Helped
- 1
- Reputation
- 2
- Reaction score
- 1
- Trophy points
- 1,288
- Activity points
- 1,887
I'm posting this here so Google (and other designers) can find it. This burned up at least a week of my time and I couldn't find *anything* about it anywhere on the web.
I have a design that is LVS-clean (using Calibre) and extracts correctly via Star-RCXT as long as calibre was NOT run with the "-hier" option. Unfortunately that's not a long-term solution because (1) the top-level design is too big to manage non-hierarchically and (2) the non-hierarchical extraction assigns different net names that no longer match the schematic.
When I run LVS with "-hier" and then extract with Star-RCXT, I get this error:
… and the extracted netlist doesn't work properly. The first node above (gnd:60) is a P-Well polygon and the rest are NFET drains (diffusion), so I wind up with a very high-impedance path from the NFET drain through the virtual shorting-transistor through the well to the well tap and then up to metal -- definitely inaccurate simulation and malfunctioning circuit.
If I flatten the layout in my layout tool (i.e. one huge GDS cell with all the polygons) that also solves the problem, but that isn't a viable long-term solution either
Ultimately I found the solution that worked: add
to the LVS deck, where "cellName" is the name of the layout cell where this problem occurs. Everything works perfectly after that. Note that "FLATTEN INSIDE CELL" is not the same thing as "LVS FLATTEN INSIDE CELL", and that the latter does not fix the problem.
This is probably a bug in either Calibre or Star-RCXT, but I don't feel like wasting my time with vendor finger-pointing; I'm sure each company will claim the other one is at fault. I don't have time for that garbage.
Hope this saves somebody else some time.
I have a design that is LVS-clean (using Calibre) and extracts correctly via Star-RCXT as long as calibre was NOT run with the "-hier" option. Unfortunately that's not a long-term solution because (1) the top-level design is too big to manage non-hierarchically and (2) the non-hierarchical extraction assigns different net names that no longer match the schematic.
When I run LVS with "-hier" and then extract with Star-RCXT, I get this error:
Code:
FOUND OPENS
There are "OPEN NETS".
"Open nets" have the same net name/number however not resistively connected;
they are formed by more than one "Resistively Connected Groups" (RCGs).
You can find the open net names below.
StarRC will never be able to determine where the source of an open net is. as such,
StarRC has randomly chosen nodes on the open net between which a shorting ressistor
will be inserted. The coordinates listed in this file for the shorting resistors will
vary based on the settings for REDUCTION, REDUCTION_MAX_DELAY_ERROR, MODE, EXTRACTION.
OPEN net: gnd (5 RCGs) :
shorting resistor: R7401 (resistance=0.01,width=100) is inserted between nodes gnd:60 (located at (-4480,15780)) and gnd:1210 (located at (7330,-8260))
shorting resistor: R12829 (resistance=0.01,width=100) is inserted between nodes gnd:963 (located at (7330,15120)) and gnd:1031 (located at (7330,8640))
shorting resistor: R12889 (resistance=0.01,width=100) is inserted between nodes gnd:992 (located at (7330,-1360)) and gnd:1031 (located at (7330,8640))
shorting resistor: R12890 (resistance=0.01,width=100) is inserted between nodes gnd:992 (located at (7330,-1360)) and gnd:1210 (located at (7330,-8260))… and the extracted netlist doesn't work properly. The first node above (gnd:60) is a P-Well polygon and the rest are NFET drains (diffusion), so I wind up with a very high-impedance path from the NFET drain through the virtual shorting-transistor through the well to the well tap and then up to metal -- definitely inaccurate simulation and malfunctioning circuit.
If I flatten the layout in my layout tool (i.e. one huge GDS cell with all the polygons) that also solves the problem, but that isn't a viable long-term solution either
Ultimately I found the solution that worked: add
Code:
FLATTEN INSIDE CELL cellNameto the LVS deck, where "cellName" is the name of the layout cell where this problem occurs. Everything works perfectly after that. Note that "FLATTEN INSIDE CELL" is not the same thing as "LVS FLATTEN INSIDE CELL", and that the latter does not fix the problem.
This is probably a bug in either Calibre or Star-RCXT, but I don't feel like wasting my time with vendor finger-pointing; I'm sure each company will claim the other one is at fault. I don't have time for that garbage.
Hope this saves somebody else some time.
Last edited: