Jul 8, 2022 #1 L Livpsy Newbie Joined Jul 2, 2022 Messages 5 Helped 0 Reputation 0 Reaction score 0 Trophy points 1 Activity points 43 Hello. I am designing a vco in cadence for 40 G applications. I run the calibre pex in order to view the paracitics. Do i choose gate level extraction or transistor level extraction? . As i know transistor level counts double paracitics
Hello. I am designing a vco in cadence for 40 G applications. I run the calibre pex in order to view the paracitics. Do i choose gate level extraction or transistor level extraction? . As i know transistor level counts double paracitics