lhlbluesky
Banned
first, thanks everyone who give me help these days.
now, i still have some problem. in pre-simulation, my circuit can work well. but when i extracted PEX netlist in calibre, and do layout post-simulation with the extracted netlist (with spectre), i find that, some modules' performance has some degree decrease, for ex: accuracy from 11bit to 10bit; and some modules' performance has severe decrease, for ex: for a buffer, input of 1.5V relating output of only 800mV, why?
i want to know which nets or parastic R or C affected the circuit performace, but the PEX netlist is too complicated, and with too many parasitic resisitors and capacitors, and i find their value not very large, in general, cap < 1fF, res < 40ohm
, however, what is the reason for my post-simulation?
here are some warnings and notices;
for PEX netlist, there are the following warnings:
pin not connected for cell AMP_1 (30) local nn=18 net num=10 pin_layer=593 seed_layer=18;
like this, they exist in many places.
for post-simulation output log:
only one connection to the following 5 nodes:
I89.XI0/XI58/N0
I89.XI2/XI22/net037
I89.XI2/XT21/N0
I89.XI2/XI48/N0
I89.XI2/XI30/N0
however, i checkd these nddes in layout, they connect well, and lvs is ok. but what is the reason, can anyone give me some advice?
i doubt that the way i extract the netlist has some problem, but i'm not sure.
besides, for calibreview post-simulation, what's the related procedure, can anyone give me some related paper or books?
thanks all. expected for answers.
now, i still have some problem. in pre-simulation, my circuit can work well. but when i extracted PEX netlist in calibre, and do layout post-simulation with the extracted netlist (with spectre), i find that, some modules' performance has some degree decrease, for ex: accuracy from 11bit to 10bit; and some modules' performance has severe decrease, for ex: for a buffer, input of 1.5V relating output of only 800mV, why?
i want to know which nets or parastic R or C affected the circuit performace, but the PEX netlist is too complicated, and with too many parasitic resisitors and capacitors, and i find their value not very large, in general, cap < 1fF, res < 40ohm
, however, what is the reason for my post-simulation?
here are some warnings and notices;
for PEX netlist, there are the following warnings:
pin not connected for cell AMP_1 (30) local nn=18 net num=10 pin_layer=593 seed_layer=18;
like this, they exist in many places.
for post-simulation output log:
only one connection to the following 5 nodes:
I89.XI0/XI58/N0
I89.XI2/XI22/net037
I89.XI2/XT21/N0
I89.XI2/XI48/N0
I89.XI2/XI30/N0
however, i checkd these nddes in layout, they connect well, and lvs is ok. but what is the reason, can anyone give me some advice?
i doubt that the way i extract the netlist has some problem, but i'm not sure.
besides, for calibreview post-simulation, what's the related procedure, can anyone give me some related paper or books?
thanks all. expected for answers.