ahmad898
Junior Member level 3
Ok I finally managed to extract the pex netlist out of calibre that matches with my verilog netlist. But, there is still one poblem. The netlist extracted from pex in spef format has changed port names with uppercase letter and this leads to the mismatch error in primeTime. My question is that what kind of setting I need to apply to calibre to aviod such change. You can see the output spef file generated by calibre pex whereas my verilog netlist is different in letters.
/// calibre pex netlist
*NAME_MAP
*1 B
*2 A
*3 CARRY
*4 MYOUT
*5 SUM
*6 C
*7 N5
*8 N6
//verilog netlist
module logic (
a,
b,
c,
sum,
carry,
Myout);
input a;
input b;
input c;
output sum;
output carry;
output Myout;
// Internal wires
wire n5;
wire n6;
wire n7;
wire n8;
/// calibre pex netlist
*NAME_MAP
*1 B
*2 A
*3 CARRY
*4 MYOUT
*5 SUM
*6 C
*7 N5
*8 N6
//verilog netlist
module logic (
a,
b,
c,
sum,
carry,
Myout);
input a;
input b;
input c;
output sum;
output carry;
output Myout;
// Internal wires
wire n5;
wire n6;
wire n7;
wire n8;