snfvsd
Junior Member level 1
Hi All,
I am trying to do top level CALIBRE LVS for a mixed signal chip. The digital block netlist (created by PNR tool) returns a netlist in which the standard cells use VDD! and VSS! notation, for e.g. a cellnetlist from the standard cell library does does not have power pins defined in the cell pins. In the analog block I just use VDDD and GNDD.
Currently I get incorrect port errors and CALIBRE finds VSS!, VDD! in the source but not in layout (in the top digital layout I have connected digital power to VDDD and GNDD). My feeling is that I have to somehow edit the netlist to map GNDD to VSS! and VDDD to VDD!. I have already tried to add this to the cdl netlist:
.GLOBAL VDD! VSS!
.CONNECT VSS! GNDD
.GLOBAL VDD! VDDD
Any ideas will be helpful!
I am trying to do top level CALIBRE LVS for a mixed signal chip. The digital block netlist (created by PNR tool) returns a netlist in which the standard cells use VDD! and VSS! notation, for e.g. a cellnetlist from the standard cell library does does not have power pins defined in the cell pins. In the analog block I just use VDDD and GNDD.
Currently I get incorrect port errors and CALIBRE finds VSS!, VDD! in the source but not in layout (in the top digital layout I have connected digital power to VDDD and GNDD). My feeling is that I have to somehow edit the netlist to map GNDD to VSS! and VDDD to VDD!. I have already tried to add this to the cdl netlist:
.GLOBAL VDD! VSS!
.CONNECT VSS! GNDD
.GLOBAL VDD! VDDD
Any ideas will be helpful!