Calibre LVS for std cell lib - "nothing in layout"

[mzquarter]

Hi everyone,

I'm trying to get Calibre LVS to work with digital standard cells, but I've hit a wall. Currently, DRC, LVS and PEX work properly with a full analog custom design created in icfb 5.1.41. However, if I do a LVS on a digital design that has only an inverter from the std cell library, I get a "nothing in layout" error. I get the same result in calibre 2008.3_34.24 and 2009.4_31.27.

Here is what I have done up to now:

1- Copied the partial library for std cells containing the symbol and schematic views (the schematics contain only pins for LVS).

2- Imported the .lef file to create the abstract views.

3- Created a schematic with an inverter symbol from the std cells, an input and an output.

4- Created a layout with the inverter abstract view instance, two rectangles of metal1 (for input and output), added the proper labels for pin/net names (as I did for the analog design).

5- Created a black box list for the LVS. The file contains a line for each cell : "LVS BOX CellName"

6- Added an include directive in my LVS .cal rule file in the include section: "INCLUDE $PATH_TO_CELL_LIST/CellList.lvs"

7- Checked PIPut for warnings or errors (tested the mapping file on the full analog design, but might be incomplete?).

8- In Virtuoso layout, filled out the calibre layout and netlist export settings.

9- Start Calibre LVS, choose Hierarchical LVS, Layout vs Netlist (default), and run LVS.

The gds file and netlist seem to be generated properly, but I get the "nothing in layout error". To double check, I streamed in the gds made for the LVS in an empty library in Virtuoso, but everything seemed to be there. My feeling is that the black box settings are incomplete and/or the std cell pins are missing in the gds... When I look at the imported std cell, it no longer has any pin/label information.

Where did I omit a step? Please assume basic experience with Cadence / Calibre.

And a side question: if I want to simulate (with parasitics) a mixed signal circuit built with custom analog parts and standard cells, and use back-annotation for the digital parts, do I need a ADMS licence for PEX? (I would think so).

 

[cop02ia]

Re: Calibre LVS for std cell lib - "nothing in layout&a

Hi,

Just some questions to help with troubleshooting:
1) Did you try using standard cell gds given by the foundry?
This is because if you create abstract data, the layers used may not be appropriate - abstraction AFAIK is used to create LEF data for digital design, which only uses interconnect (no substrate) layers. You might want to check complete gds from the foundry.
If you only want to check interconnects, I suggest using the gds from the foundry & blackboxing devices.

2) Did you map layers to include label recognition?
Try to consider how LVS derives net info. When going through PIPO, layers which are not defined may be dropped - how about text data?

3) Is blackbox necessary?
Are you blackboxing devices in the standard cells or whole standard cells? If you're checking standard cells, you shouldn't be blackboxing whole standard cells because the tool will "skip" the standard cell, hence, blackboxing it.

4)How does Calibre recognise pins?
You need to check the LVS rulefile. You might be using incorrect layers for pins/labels.

Best regards.

 

[mzquarter]

Re: Calibre LVS for std cell lib - "nothing in layout&a

Hi,

Thank you for your questions and remarks, it gave me very good hints to work on the problem. I've made some good progress on the issue, and here is what's changed.

Black box list:

My black box list file was incorrect. I had generated it from a file containing all the cell names. However, the list had the "LT" tag appended to every cell (the kit contains two versions of every cells, but only 1 cell list). Because of this, Calibre did not find the cells I was using.

After this, I no longer had the "nothing in layout" error. But of course, yet unseen problems appeared! For one, the port names were not detected. I did find a work-around (see answer #2), but I don't think the solution is ideal. More on this later. Let me answer your first questions.

1- std cell layout gds

In all our previous flows, we did not have access to the layout gds, only abstract views. I did not realize you could do black boxes on fully populated cells. I imported the gds and the LVS worked fine, with and without black box usage, except for one small annoying detail (see pin order problem after asnwer #4). We still want to keep a functional workflow using abstract views, if we can.

2- Map layers with label recognition

The only layer that is not exported is prBoundary, which I assume is safe to ignore (for automated P&R alignment, from what I understand). The text layer was exported, but I did not see any LVS rule to attach it with the metal layers. I tried to write one using the ATTACH or LAYER ORDER keywords ("ATTACH TXT Metal1"), but got an error ("cannot establish connectivity of this layer in the DIRECT connectivity set: Metal1") and quite frankly that was guesswork. Instead, I changed my streamout map file and translated the text:drawing layer with the same layer and datatype values as the metal1:label layer. This worked, but I think I'd rather have a clean LVS rule to do this in the long run. What do I need to write this rule?

3- I'm not doing the LVS for cells themselves, but for the connections between them. We're planning on mixing the digital cells with some cutom analog cells, so I think black boxes are good to simplify and accelerate LVS.

4- Calibre sees pins with the metalN:label layer (validated with the analog LVS). See answer #2 for detail/extra question.


Having imported the gds layout, I also worked on LVS without black box (which we plan to use before tape-out). In the global netlist generated from the schematics in Virtuoso, I include a cdl netlist file for the cell contents. It works, except that the pin order does not match the one generated by the Cdlout.

My guess is that the pins follow the order in the empty schematic I use as a view list for the netlist export. Furthermore, I also noticed that the pin order is also different between the cdl and the verilog file (i.e., the CK and D pins on DFFs are switched). I am worried this will affect mixed-signal simulation netlisting in spectreVerilog (I have seen this swap problem before in another technology package we use here).

I'm still not sure how to fix this one. I wanted to import the cdl file itself as netlist (File-->Import-->CDL), but I'm having problems , because for some reason it wants to find a pfet/nfet->symbol view instead of the pmos/nmos specified in the cdl file and available in my reference library. It then creates an empty mos->netlist cellview which is unusable.

So I have two seen problems left: text layer LVS rule and pin order for netlisting. I have no other ideas for the LVS pin problem (point 2). For the pin order, I will try to recreate the pin-only schematic or netlist using some other means, and will post an update if I find some kind of workaround. In the mean time, any other ideas are welcome.

Again, thanks for the tips,

Cheers!

 

[cop02ia]

Re: Calibre LVS for std cell lib - "nothing in layout&a

I think blackboxing abstract cells would be ok provided there is no interconnect layers running over the cells, but better run hierarchical on full gds of digital cells, you never know if a floating metal1 got left on top of a standard cell.

As for label recognition, I'll have to check the documentation first as I can't remember how it is done.

Usually I use the spice netlist of the standard cells for digital LVS and only the schematic when using custom layout, but I haven't encountered netlist pin order problems so far.

 

[mzquarter]

Re: Calibre LVS for std cell lib - "nothing in layout&a

For the netlist pin order, I just noticed something.

In CIW --> Tools --> CDF --> Edit, in the simulation information for the digital cells, there is no information whatsoever for the auCdl "simulator" (or any other field for that matter), compared to the library from another technology node.

I filled the fields manually for my test cell using the other tech library cells as a template, and pin order was corrected.

Now I have to figure out a way to do this with skill code to fill out every cell automatically... After that, I have a small digital design built with encounter I can use to see if it works on a larger design.

 

[cop02ia]

Re: Calibre LVS for std cell lib - "nothing in layout&a

Forgot to mention - try get some help regarding the netlists from:

https://groups.google.com.my/group/comp.cad.cadence/