NOmalum
Newbie level 3
![Newbie level 3](/styles/images/ranks/alevel3.gif)
I've installed new PDK with same technology tsmc 0.13 um.
The only thing changed was MIM capacitor to lower density capacitor from "1.5fF_MIM" to "1.0fF_MIM".
When I copied the schematic and checked the Calibre LVS, the error came out is:
bad component subtype:
layout | source
------------------
MN(N2) | MN(ND)
But this is not occured with "1.5_MIM" capacitor PDK.
I don't know exactly what is causing this descrepancy.
And I changed the fule file for "1.0fF_MIM" cap when I checked it.
Does it mean that rule file causing some mismatch? and if it is how to fix it?
Thank you!
The only thing changed was MIM capacitor to lower density capacitor from "1.5fF_MIM" to "1.0fF_MIM".
When I copied the schematic and checked the Calibre LVS, the error came out is:
bad component subtype:
layout | source
------------------
MN(N2) | MN(ND)
But this is not occured with "1.5_MIM" capacitor PDK.
I don't know exactly what is causing this descrepancy.
And I changed the fule file for "1.0fF_MIM" cap when I checked it.
Does it mean that rule file causing some mismatch? and if it is how to fix it?
Thank you!