Calibre LVS and extraction

[pokemonstation]

calibre lvs

Hello all,

I am having trouble with Calibre LVS. My problem is that Calibre LVS does not recognize the pins I placed in the layout. For example, in an inverter my schematic has 4 ports (in, out, vdd!, gnd!) but Calibre LVS states that my layout has 0 port, despite I labeled all 4 ports in the layout. I have tried to use Create -> Pin or Create -> Label to label pins in my layout, but none of them works. Does anyone know what I should do to label pins in my layout so they are recognized by Calibre LVS?

My second problem is with Calibre extraction (PEX). I was able to extract a netlist with parasitic capacitance and resistance, but the pins/nets in the resulting netlist are not labeled as I wanted in my schematic, despite I specifically set the extraction option to use schematic nets. Does anyone know a solution to this? Do I have to have a successful and error-free LVS run in order for this to work?

Thanks in advanced!

 

[deepak242003]

calibre lvs diode

Calibre LVS does not recognize the pins I placed in the layout.

Two possibilities:
1) all the labels shorted bye mistake.
2) wrong layer selected for label....use pin or tt layer for label which tool you are using..?

Do I have to have a successful and error-free LVS run in order for this to work?

yes.

Added after 46 seconds:

any other errors your are getting from lvs?

 

[ksj116]

calibre extraction

yes, the first problem is solved by checking whether your label layer is consistent with the metal layer wiring line.

 

[pokemonstation]

calibre lvs diode between vdd gnd

hello, thanks both for your replies.

I am using Cadence Virtuoso IC 6.1.3 layout editor. I am fairly sure that I selected the right material in the LSW before I place pins/labels. For example, my VDD and ground rails are on metal 1, so I select "M1: drw" before I create pins/labels. I did try the Pin layer "M1: pin" but it didn't work. What's tt layer though?

I think this is the only LVS error I had; # of instances and device parameters all matched.

 

[erikl]

lvs and extraction

What's tt layer though?

text , I'd guess

 

[pokemonstation]

calibre lvs recognize pins

Actually, LVS is working now! I guess depending on the PDK (I am using IBM 65nm cmos10lpe), the layer needed might be different. Turned out that I have to Create -> Label with the "lbl" (label) layer with the matching metal/poly.

I also disabled the environment variable PEX_RUN = TRUE, which always creates a diode between VDD and ground rail (and forces me to add a diode in my schematic)

Still, with a working LVS, I still cannot get the parasitic extracted netlist to use the net names from either the schematic or the layout. Does anyone know solutions to this?

 

[erikl]

lvs extarction using calibre

Actually, LVS is working now! I guess depending on the PDK (I am using IBM 65nm cmos10lpe), the layer needed might be different. Turned out that I have to Create -> Label with the "lbl" (label) layer with the matching metal/poly.

I also disabled the environment variable PEX_RUN = TRUE, which always creates a diode between VDD and ground rail (and forces me to add a diode in my schematic)

Still, with a working LVS, I still cannot get the parasitic extracted netlist to use the net names from either the schematic or the layout. Does anyone know solutions to this?

Thank you for your back-info! Perhaps the following note might help?
Especially the paragraph: "In the simulation information section ..." (case sensitivity of node & model names).

 

[deepak242003]

calibre lvs schematic viewer

tt layer we had used for creating labels (pins) for umc90..

 

[Usman Hai]

Hi erikl,
In your pdf, you mentioned "Now, within ADE add the netlist to the model setup". I dont understand this point. Can you please elaborate on this point.
Also, do you have experience using calibreview. I got the extracted view from the layout in calibre format. But the calibre view gave the schematic with like 513 errors all are like "No default connection..." or "could not find mapping file pin...". I am using the cell map given in the cmrf8sf kit.
Thanks in advance.

 

[erikl]

"Now, within ADE add the netlist to the model setup".
I dont understand this point. Can you please elaborate on this point.

Hi Usman,
in the ADE window, via Setup select Model Libraries .... In this window add the full path of the extracted netlist to the standard model setup.

Also, do you have experience using calibreview.

Sorry, no. I've just used the extracted netlist(s) for postLayout simulation.

Happy New Year! erikl

 

[ansonyeap]

Hi erikl,

I having problem understanding the pdf you given. Can you suggest any more details reference or guides? thank you...

 

[erikl]

Can you suggest any more details reference or guides? thank you...

See this thread! **broken link removed**

 

[rfrfrf]

hi erikl

thanks, your info was helpful for me

 

[ansonyeap]

thank you for the reply. I have a glanced at the guide and there didn't talk about calibre xRC, parasitic extraction and post-layout simulation.... where can i find the information? thank again.

 

[erikl]

... calibre xRC, parasitic extraction and post-layout simulation.... where can i find the information?

Try here!

 

[lhmdxx]

... calibre xRC, parasitic extraction and post-layout simulation.... where can i find the information?

Try here!

Thank you ,i need it now.

 

[ppboyindream]

Yes, I have the sampe question mentioned here, I use the layer ll

 

[xaxtel]

you have to see in LVS deck which layer are used to represent pin. It could be tt or lvs or pin.