Calculation of parallel feedback for oscillator design

[gecky]

Oscillator design procedure requires one to match the terminating port such that the input reflection coefficient, gamma-in > 1.

How to calculate if a parallel feedback circuit has provided a loading that met this requirement? (feedback path is between drain & gate of a FET)

I'm designing a DRO with parallel feedback for its merit of conversion gain. I'm also looking for a model of a dielectric resonator coupled to 2 microstriplines (see my previous posts).

Thanks!

 

[DJ]

The negative resistance or the reflection coeficient >1 is for 1 port circuit. For example if you design a DRO that the DR is coupled to the Gate port and the source is loaded by a capacitor when the output coupled to the drain, you can look first at the gate, tune the source and drain loads parameters for a negative resistance at the gate port and then load the DR. Actually you have to much the DR at a special point along thr TR of the gate.
For parallel feedback (DR is coupled to Drain and Gate) you can do several things:
1. Open loop the feedback correctly (When you open the loop you change it so you have to open at high impedance point or to load the open loop correctly) and then look for G>1 and phase as needed.
2. Play with the circuit parameters and look at the load port- At the source in your case. For oscillation you will find the S11 curve all the way goes clock wise but at the oscillation frequency it change its direction and goes oposit way and again clock wise.
3. Look at an open port. For example just look at the gate port (The gate is still loaded by the DR that also coupled to the Drain.) You have to have two conditions:
a. Negative resistance (Or S11>0dB)
b. At resonance it is a parallel circuit. It means S11 goes from uper side of smit chart to the down side.
4. Use ADS simulator with Oscport or Ostest.

D.J