calculate the drain and gate capacitance

Hello...... can some body help me to find the answer of the question below? Regards

For the BSIM excerpt shown calculate the drain and gate capacitance for a 10um wide transistor in 0.35um CMOS technology.
.MODEL CMOSN NMOS ( LEVEL = 49
+VERSION = 3.1 TNOM = 27 TOX = 7.7E-9
+XJ = 1E-7 NCH = 2.2E17 VTH0 = 0.4709506
+CGDO = 2.16E-10 CGSO = 2.16E-10 CGBO = 1E-12
+CJ = 1.392104E-3 PB = 0.99 MJ = 0.5741795
+CJSW = 3.18479E-10 PBSW = 0.99 MJSW = 0.3564651
+CJSWG = 4.42E-11 PBSWG = 0.99 MJSWG = 0.3564651
+CF = 0 PVTH0 = 0.0168959 PRDSW = 143.6823497
+PK2 = 2.013494E-3 WKETA = 2.155719E-3 LKETA = 5.984014E-3

homework? ;-)

gate capacitance = CGDO + CGSO + CGBO ; all 3 in parallel
drain capacitance = (CGDO * CGBO) / (CGDO + CGBO) ; these 2 in series

These cap values are given in F/m , so you have to calculate them for overlap length (2*length) .

Thanks a lot for your reply. Yes its home work

You initially wrote that I have to calculate for a periphery (width+2x Length) ...Please explain this

Now you have corrected for (2 * L).........Please explain this

Can you give me some reference. Regards

s_ss said:

Now you have corrected for (2 * L).........Please explain this

Click to expand...

I was wrong again, sorry! These are overlap cap parameters from gate to bulk, source, or drain, and this overlap exists just for one length for CGSO and CGDO, but for both lengths of the transistor for CGBO.

s_ss said:

Can you give me some reference.

Click to expand...

See e.g. this **broken link removed**, which describes all SPICE parameters. Search for your parameters!

BTW, the last letter of those parameters is an "oh", not a "zero".