Calculate Effective Capacitance

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sherline123

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I was confused when calculating effective capacitance at a point. For example,
Point Y should see 2C to gnd and 4C to Vdd. Why we can make it an equivalent circuit to 6c to gnd?
For pmos parasitic cap, it always connected between output and vdd. Why we need to add this into effective capacitance since it never draw current as long as vdd is on.
 

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sherline123 said:
I was confused when calculating effective capacitance at a point. For example,
Point Y should see 2C to gnd and 4C to Vdd. Why we can make it an equivalent circuit to 6c to gnd?
Click to expand...

is there not 6C of capacitance electrically connected in parallel?

For pmos parasitic cap, it always connected between output and vdd. Why we need to add this into effective capacitance since it never draw current as long as vdd is on.
Click to expand...

How can you say the two caps are "nonswitching" when in fact that are connected to switches through a resistor? If the switches are operated ON and OFF, the capacitors will energize an de-energize, thereby affecting the circuit.

Ratch
 

Assuming the circuit in (b) is correct, the (c) circuit is the equivalent network to calculate the impedance seen from Y to ground.
 


I don't understand how to calculate effective cap referring to one point only, i thought it always need to be 2 points. Can we say they are in parallel even though they are not sharing both nodes? Yes they are switching, but cap connected to vdd should not be draw current from point Y if Y < Vdd?



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CataM said:
Assuming the circuit in (b) is correct, the (c) circuit is the equivalent network to calculate the impedance seen from Y to ground.
Click to expand...

Refering to (b), from Y to ground i thought it should be only 2c? From point Y to ground how can we conclude that they are in parallel since voltage at point Y is unknown.
Or we should calculate it like calculating thevenin resistance, shorting voltage source to gnd?
 

CataM said:
Exactly. Thevenin between Y and ground.
Click to expand...

When doing thevenin theorem, we are actually replacing the circuit with a circuit of Vth + Rth. For capacitance, we only replace the circuit with effective capacitance and there are no Vth?
 

Here is a quote of what I have already said in post #3:
....the (c) circuit is the equivalent network to calculate the impedance seen from Y to ground.
Click to expand...
That means, the (c) circuit is the equivalent circuit that computes the Thevenin impedance. How do you calculate the "Zthevenin" ? You need an equivalent network, don't you ? That is circuit (c).
 


I see. So means the voltage supply (e.g vdd) also no longer is Vdd anymore, it should become Vth?
 

So means the voltage supply (e.g vdd) also no longer is Vdd anymore, it should become Vth?
Click to expand...
No. Calculate Vth and see that Vth is different than Vdd. If Vdd is DC, Vth is simply 0, regarding Thevenin equivalent between node Y and ground.
 


Sorry, I did not notice that the upper caps were connected to ground and the lower caps were connected to a voltage source. I assumed all the caps were connected to ground. Let's look at a voltage analysis of the circuit and you can decide how the caps affect the circuit. The upper switching cap is permanently shorted, so it does not affect the analysis. Similarly, the lower cap is permanently energized to the value of the source voltage. Since the voltage varies with time, we have to find the voltage using a differential equation and solve it using Laplace transforms. Assuming all the caps are initially de-energized, and the bottom switch is open at t < 0, calculate the y voltage after the bottom switch closed at t >0.

The node equation for Y is


The Y value in the s domain is


The y value in the time domain is


Notice that at t=0, the value of the voltage source is v/3, where v is the value of the voltage source. After a sufficient time, when all the caps are energized, the voltage increases to v/2.

So, looking at v(t), you can decide what the "effective capacitance" is.

Ratch
 
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CataM said:
You did not notice either that the upper switch and lower switch can not be conducting at the same time.
Click to expand...

That is correct. There is nothing in the schematic to indicate that the two switches are coupled in that fashion. The equation I presented can easily be changed to show that situation.

Ratch
 

Ratch said:
The equation I presented can easily be changed to show that situation.
Click to expand...
Right after you correct the 2 errors your "equation I" has.

There is nothing in the schematic to indicate that the two switches are coupled in that fashion.
Click to expand...
Check circuit (a).
 

CataM said:
Right after you correct the 2 errors your "equation I" has.


Check circuit (a).
Click to expand...

Are you referring to the initial voltages on the lower caps? I wish you would be more specific. Is circuit "a" the schematic the OP submitted? It says the caps are for switching, but it does not say how the switches are operated. Please show me where it says only one switch can be ON or OFF at the same time.

Ratch
 

Are you referring to the initial voltages on the lower caps?
Click to expand...
No. Simply KCL equations are wrong, specifically, the third and fourth. Re-write KCL and you will find out. The third KCL should be multiplied by 4 and the fourth by 1.

Please show me where it says only one switch can be ON or OFF at the same time.
Click to expand...
Post #1, circuit (a) shows 2 complementary MOSFETs i.e. a P channel and a N channel. Both MOSFETs have the gates tied together and hence the same control voltage.
 

CataM said:
No. Simply KCL equations are wrong, specifically, the third and fourth. Re-write KCL and you will find out. The third KCL should be multiplied by 4 and the fourth by 1.
Click to expand...

There is one equation with four terms. The third term is for the two bottom caps of 1C each. That makes 2C. The fourth term is for the two top caps of 2C each. That makes 4C. The third and fourth terms show that. What is lacking if the initial voltages on the bottom two caps. Otherwise, I don't see any mistakes.


Post #1, circuit (a) shows 2 complementary MOSFETs i.e. a P channel and a N channel. Both MOSFETs have the gates tied together and hence the same control voltage.
Click to expand...

OK, I see that now. I only looked at the schematic. There are many different ways to diagram a mosfet, so I do not try to keep up with all the possibilities. The schematic should have shown some coupling between the two switches.

Ratch
 

Ratch said:
There is one equation with four terms. The third term is for the two bottom caps of 1C each. That makes 2C. The fourth term is for the two top caps of 2C each. That makes 4C.
Click to expand...
Wrong. The third term has subtracting V/s, which suggests it is for the upper caps. I see your mistake now. If you do not subtract V/s from the third term but you subtract it from the fourth term, then you have it correct. Note that you will have then the same as you would get by making the changes suggested in post #15.
 

CataM said:
Wrong. The third term has subtracting V/s, which suggests it is for the upper caps.
Click to expand...

The third term is for the lower caps. That is evident because the denominator is 1/Cs. If it was for the upper caps, the denominator would be 1/2Cs like it is for the fourth term. The top caps are grounded, therefore have no v/s in the numerator. The bottom caps are permanently connected to a DC voltage, therefore I should have shown an initial voltage instead of a switched voltage.

I see your mistake now. If you do not subtract V/s from the third term but you subtract it from the fourth term, then you have it correct. Note that you will have then the same as you would get by making the changes suggested in post #15.
Click to expand...

The fourth term is for the upper caps which are grounded and never see v/s. In fact, only the bottom resistor sees v/s.

Ratch
 

Hi,
We have 4C connected from node Y to VDD, and 2C connected from node Y to gnd. I think we can all agree on this.
To calculate the output impedance of the circuit we connect to the output a source, let's say a voltage source, and we measure the current drawn from it. But in this process all other voltage sources become shorted and current sources become open circuit. This means that the voltage source, VDD, is replaced by a short circuit to ground. Now the 4C connected previously to VDD are connected to ground. Since the 2C are also connected to ground we obtain a total of 6C connected to ground.

From above discussion we can see that the 4C are not phisicaly connected to ground, but they modeled as so when we do a small signal analysis.

Hope this helps.
 
Seems like your definition of top and bottom is different than mine.
For me, bottom caps are those which are connected between Y and ground, that is, 2C.
The top caps are those which are connected between Y and VDD and hence have a voltage across them of Y-V/s. Those are 4C.

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I see now, you are taking the GND and VDD symbols exactly opposite than I.
You are correct using your terminology, sorry for the misunderstanding.
 

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