Cadence Virtuoso IC6.1.5 version

Respected Sir,

I am working on a ASIC on Cadence design tool in M.tech Level in my College.
Till Now I was Coding in VHDL and successfully simulate it.Now I have to design schematic,layout LVS,RCX and all that post layout simulation work on Cadence tool so that to complete my thesis.

My circuit as I get from Technology schematics on Xilinx tool (Using VHDl as i told) is very large and complex.

I just want to know about,if there is any method,any utility in cadence to get schematic from VHDL code directly.and no need to draw it manually in cadence.
I was trying to import VHDL code in it but it autodesign a symbol only .By which I am unable to design layout and all that later work.So please suggest me.If any such tool available in cadence.

Version of cadence i am using is Virtuoso IC6.1.5 Schematic composer etc.

on RedHat linux

You will have to existing standard cell library to which you vhdl/verilog code synthesizes to. Once you import the gate level netlist into cadence it needs to map to the actual gate which should exist in the cadence library(if you have one). Once you get the library, then you dump the netlist and layout from the standard cell library. Usually people do the opposite, the vhdl code is synthesized into gates and using .lib/LEF/GDS and automated P&R tool the design is done.

it has nothing to cadence version as methodology wise it is supported by cadence.

thanking you sir.I will try this.

mukul032 said:

thanking you sir.I will try this.

Click to expand...

on which topic are you working

Thanking you ma'am.
I am working on ASIC for traffic light control.A single IC with lots of options available like real time synchronization,Rush Hour and night mode time setting flexibility and individual setting for each road of 4-way and 3-way crossing and many other features............

- - - Updated - - -

Actually My VHDL Code is fine and working correctly............I heard that We can directly get schematic and than layout in Cadence from VHDL code..........I tried......... but no success yet................I think that something wrong with my Cadence system library itself......I google lot of about this problem and apply those suggestion too but something is missing in my college system about library......about directory or something............I think so...........but not confirm ....... because yet I don't know the actual way of doing this conversion from VHDL to Cadence Virtuoso Schematic...................Google suggest Some kind of "Leapfrog tool"............reside in Ieee and Std library....i think both of these things are missing here..........But any way Any kind of help from You or anybody is very helpful and be fast friends...............My M.Tech Will finish in approx 1 month............Thank you so much