Cadence Virtuoso cant do Vertical Transistors???? WHAT?????

[gezzas525]

Tried laying out transistors in virtuoso, when rotating them as to make a vertial transistor the extracted layout of the nmos is connected the wrong way round, the drain is connected to ground??? and source to the output, horizontaly its fine but vertical its wrong. The pmos connects fine either way.

 

[gezzas525]

Re: Cadence Virtuoso cant do Vertical Transistors???? WHAT?

Also the gnd! and vdd! show up as inputs in the spectre simulator and not as global nets as they should be?

KLEOS

 

[gerryhsu]

Re: Cadence Virtuoso cant do Vertical Transistors???? WHAT?

Tried laying out transistors in virtuoso, when rotating them as to make a vertial transistor the extracted layout of the nmos is connected the wrong way round, the drain is connected to ground??? and source to the output, horizontaly its fine but vertical its wrong. The pmos connects fine either way.

Do you know what drain or source mean?

 

[gezzas525]

Re: Cadence Virtuoso cant do Vertical Transistors???? WHAT?

hmmmmm let me think.....lets see errrrrr yes.

Iam talking about the extracted layout, the symbol is the wrong way round when placing transistor vertically.

The other problem is that spectre wont accept vdd! you have to delete the ! but gnd! is ok, i think its a bug.

KLEO

 

[gerryhsu]

Re: Cadence Virtuoso cant do Vertical Transistors???? WHAT?

Tried laying out transistors in virtuoso, when rotating them as to make a vertial transistor the extracted layout of the nmos is connected the wrong way round, the drain is connected to ground??? and source to the output, horizontaly its fine but vertical its wrong. The pmos connects fine either way.

NMOS transistor is formed by a poly strip cros over n diffusion area. There is no such vertical or horizontal. These concept only exist in BJT.
Do you really know what you are talking about ?

 

[okguy]

Re: Cadence Virtuoso cant do Vertical Transistors???? WHAT?

Your problem seems to come from from DIVA tech file.
Try to look at it and how the diva extraction is done.
Also have a look at your power or global nodes
(those last concept are from Dracula, I'm not sure for Diva)

 

[Hughes]

Re: Cadence Virtuoso cant do Vertical Transistors???? WHAT?

Tried laying out transistors in virtuoso, when rotating them as to make a vertial transistor the extracted layout of the nmos is connected the wrong way round, the drain is connected to ground??? and source to the output, horizontaly its fine but vertical its wrong. The pmos connects fine either way.

Do you mean y-direction by "vertical"? Physically, he drain and source terminals of MOSFET are interchangeable. It is not by the symbol but by node voltage to determine which terminal is source and which is drain.

 

[gezzas525]

Re: Cadence Virtuoso cant do Vertical Transistors???? WHAT?

I dont mean physically I mean when I extracted the layout the view allows you to see symbols of each individual transistor. The problem is when the layout has the transistors vertically ie the gate is on the left or right then the symbols are drawn the wrong way round when you click gnd or vdd. The circuit simulates fine.

 

[gerryhsu]

Re: Cadence Virtuoso cant do Vertical Transistors???? WHAT?

I dont mean physically I mean when I extracted the layout the view allows you to see symbols of each individual transistor. The problem is when the layout has the transistors vertically ie the gate is on the left or right then the symbols are drawn the wrong way round when you click gnd or vdd. The circuit simulates fine.

The way you talk show that you don't know the very basic fact about MOS transistors. I don't know where to start to explain to you. Find any text book and learn again

 

[gezzas525]

Re: Cadence Virtuoso cant do Vertical Transistors???? WHAT?

I know what iam talking about, WTF is your problem? then your slaging off all my post with your own stuipid comments.

 

[buru]

Re: Cadence Virtuoso cant do Vertical Transistors???? WHAT?

I just started to work in IC5033, and i don,t know much. Please let me know what thw problem is.
Vertical MOS means
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(It is obvious that "vertical" doesn't mean verticaly in the silicon wafer, like a BJT)