Cadence: Unable to plot PAE graph

[Xxy]

Hi,
I've designed a CMOS power amplifier. I'm unable to simulate PAE graph, I've chosen all the ports, but the bottom part of the direct plot form shows ERROR: /PORT1/PLUS is not a kept output. May I know what is the error means?
Thanks.
**broken link removed**

 

[Dominik Przyborowski]

I've chosen all the ports, but the bottom part of the direct plot form shows ERROR: /PORT1/PLUS is not a kept output. May I know what is the error means?

This error looks like invalid user.
You are pointing to terminal PLUS of instance PORT1, which has not been saved as output (currents are not saved by default) or, tool require you to select port not port terminal.