cadence transient analysis convergence problem

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jszair

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Hi, I'm simulating a ota with capacitance feedback and run into convergence problem in transient analysis. DC analysis is fine. The following are simulation reports, any suggestion?


 

Try setting cmin to some reasonable value. That would be something
like 1/10 your minimum sized transistor Cgs, maybe.
 

AdvaRes said:
Increase also the simulation time.

I doubt that will help - the transient analysis is aborting prematurely anyway, most likely due to the floating node which causes a singularity.

Keith
 

What about initial conditions? Activated yes or no? Try both alternatives.
 

Cranking down simulator tolerances can help, in cases where the
problem lies with some component that has a superlinear
high voltage/current response or singular behavior outside the
normal, fitted model range. Not stepping off the cliff in the first place,
helps.

Some solution methods seem to run cleaner than others. TRAP
is fast and really easy to drive into the weeds; Euler is the most
damped and sometimes this is exactly what you need. GEAR,
somewhere in the middle.

You could go probe around in the results just before the thing
blew up, and see which nodes / ports are headed out into the kV/kA
range, and perhaps determine why. Ridiculously low capacitances
are the most common cause of timestep convergence fails
in my observation.
 
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