[CADENCE] STB simulation gives diffrent phase margin than AC simulation

[AceCraft]

Hi!

As in the title: I run two simulations and receive diffrent results.

STB testbench || STB results

phase margin: 44.51 deg @ 2.897 MHz

AC testbench || AC results

phase margin: 69.04 deg @ 3.106 MHz

Of course I've checked every parameters are the same. Furthermore from time analysis the goal circuit is behaving stable, with
no apparent ringing.

Could somebody explain me why this incoherence occurs and which results are more reliable?

With best regards,
AceCraft.

 

[LvW]

As far as the phase response is concerned - the second display obviously is wrong since it starts at -45 deg.
For low frequency the phase shift (for negativ feedback) must start at -180 deg (like in the 1st picture)

Sorry - I have used the wrong y scaling.

Unfortunately, I am not able to read your circuit drawings (bad resolution), response curves are OK.
Therefore my question:
1.) Did you select for both methods the same point to check the loop gain?
2.) How did you perform ac analysis - that means: how did you open the loop?

 

[AceCraft]

@LvW

Open image in new tab and click on it to magnify. Resolution is good.

1. I've selected same point to measure for both methods: it's IPROB for STB analysis and point between
inductor and resistances in AC.
2. I've opened the loop with 100GH inductance.

I'm pretty sure at this point that results from AC analysis are correct, while those from STB are not.
I've run time analysis with phase margin from AC near 45 deg and at that point circuit starts to
generate.

 

[LvW]

I'm pretty sure at this point that results from AC analysis are correct, while those from STB are not.
I've run time analysis with phase margin from AC near 45 deg and at that point circuit starts to
generate.

Why do you think that ac is correct? The LC method you have applied does not mirror the actual load. Thus, I don't know if this matters (depends on amplifier parameters).

Question: What is the maximum group delay (and at which frequency) during normal operation of the circuit with feedback (without any additional circuitry for loop gain simulation)? From this information one can derive a rough phase margin information.

 

[AceCraft]

In my oppinion it's correct because circuit is not generating with load corresponding to phase margin 45 deg from AC simulation.

What about group delay. I've never done such analysis before so please correct me if I done it wrong.

ACgroupdelay


I used groupDelay(VF("/net37")) command, where net37 is net at point between inductor and resistances.
Can you explain me how should I acquire phase margin from group delay?

 

[LvW]

As I have mentioned: group delay for NORMAL OPERATION - that means: normal signal input and output!
Please read again: Without any additional circuitry for loop gain measurement (like the inductor)!

 

[AceCraft]

Is it correct now? Otherwise please tell me where should I put AC source

 

[LvW]

AceCraft,

no, it's not correct.
At first, some general remarks:
You have a question - and in order to enable some forum members to answer you should give some basic information.
For example:
*What is the purpose of the circuit?
*What is the circuitry within the "FET-box"?
*Are you sure about a suitable bias point (because of single supply). Did you simulate it?
*Where is the input for "normal" operation? You have shown an ac signal source connected (through a capacitor) directly into the non-inverting opamp input (that acts as a feedback input). I doubt if this is the intended configuration. What is the purpose of this capacitor?
* I repeat again: What is the maximum group delay (and at what frequency) of the circuit under NORMAL operational conditions?

 

[LvW]

I think, perhaps it's appropriate to add some explanations:
Of course, I know the purpose of the circuit (nevertheless, you should have mentioned).
And I have good reason to ask for "normal operation" because that's the key to understand the function.
It is simply a control loop that has two main tasks for "normal operation":
* The output must follow the reference voltage ("tracking control loop")
* Some fluctuations of the voltage at the pass-element must NOT appear at the output (disturbance control loop)

Both control actions can be described with a transfer function. And these transfer functions have a frequency response with a phase response and a respective group delay. At the stability limit (phase margin zero) the group delay is infinite (phase jump) and the delay becomes smaller for a rising phase margin. That is the background of my question.

 

[dgnani]

Hi!

As in the title: I run two simulations and receive diffrent results.

STB testbench || STB results
View attachment 59969 View attachment 59970
phase margin: 44.51 deg @ 2.897 MHz

AC testbench || AC results
View attachment 59971 View attachment 59972
phase margin: 69.04 deg @ 3.106 MHz

Of course I've checked every parameters are the same. Furthermore from time analysis the goal circuit is behaving stable, with
no apparent ringing.

Could somebody explain me why this incoherence occurs and which results are more reliable?

With best regards,
AceCraft.

Hi AcerCraft

see if this casts some light: **broken link removed**