Cadence simulatuon of a Class A amplifier.

[sze wen]

I have a 50ohm resistor at the output. How should I design from there.

 

[OZero57]

Well, that's not enough information to help you.... at all. What are your working with (software, device), and what are your requirements?

Check SC Cripps book on Power Amplifiers (first two chapters) and pick up Razavi RF or Sorin HF (Sorin is more design-focused in a sense than Razavi, but having a copy of both is good). I suggest Sorin since it's slightly easier to read. Check Chapter 6 for PAs, and refer to earlier chapters for more basics (chapter 1 to 4 are really good).

That said.....

Assuming an arbitrary device, generally for a Class A amplifier you want the Transistor to be On all the time or have 360 conduction angle. This is basically how most "small-signal" amplifiers (like the ones you are taught in introductory analog design) operate (always On/in Saturation). Note the distinction between small-signal amplifiers ("analog" CS/CE stages, Cascodes, OTAs, LNAs (which could be CS/CE, cascodes as well, but have different design considerations),) and large-signal amplifiers, which do not obey the small-signal approximations. Your "normal" AC simulations and S-Parameters simulations are not accurate, if at all, for power amplifiers. But for Class A amplifiers, normal S-Parameters somewhat work. Or they could be at least a starting point.

So with that knowledge, assuming you have a certain output power requirement, bias the transistor accordingly to always be in saturation for maximum power. (The details vary depending on what device you're working with (IC, discrete, technology, materials. etc)). To do that, you need to have maximum voltage and current swings across the device. Plotting the device's IV characteristics is crucial to help you with that.


(DCIV. Image Source)
With your DCIV known, you will get your optimal R value for this maximum power.

To get the best results, you have to do something called Load-pull. Basically you vary the output impedence systematically to get an optimal value for your goals. Usually, different contours of power and efficiency are plotted ona smith chart. This should help you find the optimal output impedence (which may not be exactly the Optimal R that you derive with simple hand analysis. not to mention that for actual devices, especially nanoscale FETs, your IV characteristics will not be "clean" at all!). Let's call this Zopt.

Note that sometimes, this Zopt could be known if you are using a discrete device. If you are using a nanoscale FET, especially one that's planar and strongly deviates from the square-law model, doing load-pull yourself is MUST at this point. ADS, Cadence, and the like could easily generate them. ADS is much more suited for this than Cadence Virtuoso in my opinion.

But....usually the output port has a impedence value that you have to adhere to (say 50ohm in your case), so how could I make the transistor see this value? You will need to create a matching network so that the transistor can see this Zopt at its output.

You will also need to create an input matching network to improve metrics such as your gain and minimize S11. You will also need to stabilize your amplifier (there are techniques for that as well. For example, inductive degeneration).

Normal S-parameters somewhat work for a Class A amplifier, u can take them as a starting point. But! there's no way around HB analysis and/or other analyses (PSS, PAC, LSSP, etc depending on what software you are using) to check your results, such as your PAE and Output power and compresion points or curves, which your SP-analysis won't tell you accurately if at all.

Know what harmonic balance is and understand the basic fundamentals behind it (I am not talking about the intricates of how its done, etc. But why do you even need it and what is a harmonic, etc). The above books could help. Razavi chapter 2 for example. And search on the internet. There are also youtube videos which could help.

Check the link in the source for starters as well as the books I have outlined. Take your time learning this stuff. Sit down, do your hand-analysis and apply ..... both!

(excuse any typos here and there.....)

 

[D.A.(Tony)Stewart]

NFB configurations reduce THD from quadratic effects by the amount of gain reduction from open to closed loop as long as they have phase margin from all poles in junction capacitance.
So a good design always begins with your expectations or specs.