Cadence RTL Compiler to minimize for Area

Hello all,



I am using RTL compiler to synthesize a pure combiniational digital designs. I would like to know how to constraints the synthesis tool to minimize the Area as its first periority or even may be the only periority.



The shell script I use to synthesis my designs is:

#/bin/sh

SYN_ID=$2

FILE=$1

SYN_TOOL=rc

RC_REPORT=/tmp/syn.$SYN_ID.rpt

AREA=/tmp/syn.$SYN_ID.area

$SYN_TOOL > $RC_REPORT << EOF

set_attribute lib_search_path ../../../Digital_Standard_Cell_Library/synopsys/models

set_attribute library {saed90nm_typ.lib}

read_hdl $FILE

set_attribute avoid true LNANDX1 LNANDX2

elaborate

synthesize -to_generic

synthesize -to_mapped

synthesize -to_mapped

synthesize -to_mapped

synthesize -to_mapped

synthesize -to_mapped -effort high

write_hdl -mapped > /tmp/syn.$SYN_ID.v

echo [get_attribute area /designs/*]> $AREA

quit

EOF

How can I constraint the RC to minimize the area as much as possible?

Alos, I have some designs that desribes in truth tables format (Berkeley PLA format), How can I read these designs with cadence?



Thanks a lot.