Jan 13, 2013 #1 V vickyskarthik Newbie level 1 Joined Jan 12, 2013 Messages 1 Helped 0 Reputation 0 Reaction score 1 Trophy points 1,281 Activity points 1,285 I have designed an 8 bit SAR ADC using Cadence virtuoso. I have designed the layout of the comparator and DAC and extracted the parasitic components. What are the methods by which i can reduce the parasitic components?
I have designed an 8 bit SAR ADC using Cadence virtuoso. I have designed the layout of the comparator and DAC and extracted the parasitic components. What are the methods by which i can reduce the parasitic components?