TonyLS
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I have a netlist generated with Cadence/Genus and want to do a LEC compare (RTL Vs. Netlist) using the Synopsys Formality logic equivalency checking tool. It's likely I will need guidance coming out of the Genus synthesis tool, (similarly how SVF files from dc_compiler is passed to Formality). Is there a way to pass Cadence/Genus guidance files to Synopsys Formality?
Thanks
Thanks