Cadence - MIMcaps become unrecognised after introduction of a new component

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BartasA

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Hi,

I have a really weird issue with the layout of my design (TSMC 0.18um BCD). I have three components (A, B and C), all of which are LVS and DRC clean and sitting in their own respectable NBL. Component A has a large MIMcap (multiplier 60) with a 1.8V, 5 V, floating 5V and HV inputs, B is a logic block at 1.8V, and component C has two separate 1.8 V supplies (AVDD and DVDD) and is covered by MIMcap as well. Now I am making a higher level component D that includes A, B and C together.

My issue is that although components A, B and C are all DRC/LVS clean, after I instantiated A, B, C in component D, all of the MIMcaps of A become not recognised in the schematic. I could not initially find the issue so I did the following in the schematic and layout:

1. Instantiated only A with all ports NC. Result: LVS clean
2. Added supply pins to A. Result: LVS clean.
3. Added all other pins apart from the ones that should come from B and C. Result: LVS clean.
3. Include component B and connect to A. Result: MIMcap not recognised. >> I then pinpointed this to having VSS of A (5V NBL) connected to VSS of B (1V8 NBL). Really not sure why this is an issue...
3.b Create a separate ground pin for A and B. Result: LVS clean.

At this point I have LVS clean and continue with the incremental approach:
4. Instantiate C with all pins except substrate NC. Place it anywhere in the layout away from A and B + connect SUB through M1. Result: LVS not clean, MIMcaps not recognised in the schematic and all nodes related to these capacitors not recognised correctly either.

Does anyone know what could cause such an error when all components are LVS clean? Where could I find a clue about this?
Does anyone have any ideas why having VSS connected (point 3) and adding a new component (point 4) results in the same error?

One thing to note here is that the MIMcap in A is a bootstrapped capacitor that generates a floating 5 V supply, but I do not see the direct link of it being the issue...

Any help is highly appreciated!
 

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Look to your supply nets and the plates used in each. Caps may be
getting pruned as shorted, or shorting may fail the extraction logic.

Like say A and C used M6 vdd and M5 vss, but B used M6 vss and
M5 vdd (or one of your various).

Probe the nets that are supposed to be attached to the "missing"
caps and see what highlights. Too little? Too much? Both plates,
indicating a short? And maybe because MIM is just metal terminal
short rules are not applied. Or maybe they were reported and you
didn't notice.
 

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Also look to cell butting, and any possibility that the plates of
two separate cells, may "merge" when co-placed and then two
separate MIMs become one flat-extracted oversized cap while
the "other one" is subsumed in the first?

If your cell which still has MIMs, is delivering size error as if it's
extra fat, this could be it.
 

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UPDATE:
I have been analysing the issue and found the possible culprit: I have a subcomponent of A that includes a MIMcap with a multiplier of 60. The LVS of this subcomponent is correct, but the LVS includes a list of "Ambiguity Resolution Points", all of which are these MIMcaps. This is strange because the top and bottom plates are connected to ports, and the layout instances are matched to the schematic when checking component correspondence in Layout XL. In any case, this subcomponent fails LVS later when I run the LVS for the full component D.

Based on the information on the internet, if there are too many ambiguities, LVS errors can arise moving forward. I have two ideas:
1. It seems it is possible to assign nodes one to the other, but I am not sure how to do it.
2. I bring the top/bottom plates as ports upwards in hierarchy to component D, hoping it would change something.

Does anyone know of the best way to remove ambiguity on the lower hierarchy level?
 

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It might help if you deduced the -nature- or the -why?- of these
"ambiguities". What's it confused about really?

Highly repetitive series / parallel networks (like, say, each MIM
has a FET in series, and you are paralleling at the "stack level")
creates a sea of identical-at-first-look mid-nodes which have
no schematic representation other than auto-assigned names
from the flattening. Any topological differences to distinguish
by, are remote in the circuitry.
 

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I managed to solve the issue:
1. Firstly, I made the capacitor (m=60) as a separate component and removed it from A. I then brought the capacitor in D. This resulted in LVS having two errors instead of 60 for the capacitor.
2. The two MIMcaps that were the problem at this point were placed above a circuit and not recognised as capacitors. I moved them away and the LVS got finally clean.

I wonder if those two capacitors were the main culprit in the original configuration...
 

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Mildly surprising that "circuit under MIM" would cause a
problem, the technologies I've used did not (MIM caps
being 4+ levels up the metal stack, and somewhat
planarized ILDs I reckon).

But perhaps there are "logic bombs" when "recognition"
features coincide, or something?

Might eyeball design kit docs for MIM layout limitations
and whether you're getting bit by something that "should
be OK", or "never was".

But then how did you pass lower level cells before? Was
MIM over "white space" until you butted them up?
 

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