supremekai
Newbie level 2
![Newbie level 2](/styles/images/ranks/alevel2.gif)
Hello guys,
I'm new on Cadence and I'm designing the layout of an OTA and on the LVS I have encountered the following message: "Unmatched Internal Nets" I think regarding the connection between:
->The bulk and the vdd! of the transistors (WHITE on the image)
->The connection between the bulk and the com_diff net (BLUE on the image)
The images of the schematic and layout (regarding LVS) are the following:
![schematic-lvs.png schematic-lvs.png](https://www.edaboard.com/data/attachments/53/53457-7ecad18ffb862db18d737f6874fc3354.jpg)
![layout-lvs.png layout-lvs.png](https://www.edaboard.com/data/attachments/53/53458-0851f8c0f01909e3ae5f59abea4e61a0.jpg)
How can I join correctly the bulk with vdd! and com_diff nets? Is some contact needed?
Thank you very much in advance!![Smile :) :)](data:image/gif;base64,R0lGODlhAQABAIAAAAAAAP///yH5BAEAAAAALAAAAAABAAEAAAIBRAA7)
I'm new on Cadence and I'm designing the layout of an OTA and on the LVS I have encountered the following message: "Unmatched Internal Nets" I think regarding the connection between:
->The bulk and the vdd! of the transistors (WHITE on the image)
->The connection between the bulk and the com_diff net (BLUE on the image)
The images of the schematic and layout (regarding LVS) are the following:
![schematic-lvs.png schematic-lvs.png](https://www.edaboard.com/data/attachments/53/53457-7ecad18ffb862db18d737f6874fc3354.jpg)
![layout-lvs.png layout-lvs.png](https://www.edaboard.com/data/attachments/53/53458-0851f8c0f01909e3ae5f59abea4e61a0.jpg)
How can I join correctly the bulk with vdd! and com_diff nets? Is some contact needed?
Thank you very much in advance!