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Cadence "LVS Failed" Error

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Terp

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Hi All,

I posted this question yesterday, but it looks like it got lost somewhere. So, here it is again...

I simulated my voltage comparator schematic without glitches, got the layout done, and got it to pass the DRC checks, successfully extracted (I think...) the layout. But, when I run LVS, it terminates, displaying on the screen : "..... LVS Failed."

I checked my output log file, and found
"........ AEL's Message: Missing CDF Parameter" under schematic netlisting for all of my MOSFETs. So, then, I went ahead and made sure that my lambda was specified under CDF page, and re-ran the schematic simulation, which turned up no errors. But the LVS still fails, and the output log file still displays that message.

I would appreciate any help/suggestions on what my debugging steps should be.

Thanks, and best regards!

Added after 49 minutes:

An Update:

I just got the LVS run to succeed, and my netlists match as well.
 

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