jhallows
Member level 5
Hey I was wondering if anyone can confirm if this is a bug or just my computer has the problem.
Synopsis: Cadence Logic, Design, and Verification (LDV) 3.3, 5.0, 5.1 crashes Orcad 10.0
Platform affected: Orcad 10.0, Orcad 10.0 with SP 1.1, Orcad 10.0 with SP 2.0
O/S Type; Windows XP with SP 1a
Description of problem:
While completing steps in the tutorial for Xilinx FPGA project flow, (**broken link removed**), Signalscan crashes the Orcad Capture while either expanding signals, (LDV 3.3) or while selecting signals (LDV 5.0, 5.1). Orcad Capture displays the error message, "Exception access violation error".
Thanks.
Synopsis: Cadence Logic, Design, and Verification (LDV) 3.3, 5.0, 5.1 crashes Orcad 10.0
Platform affected: Orcad 10.0, Orcad 10.0 with SP 1.1, Orcad 10.0 with SP 2.0
O/S Type; Windows XP with SP 1a
Description of problem:
While completing steps in the tutorial for Xilinx FPGA project flow, (**broken link removed**), Signalscan crashes the Orcad Capture while either expanding signals, (LDV 3.3) or while selecting signals (LDV 5.0, 5.1). Orcad Capture displays the error message, "Exception access violation error".
Thanks.