Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

cadence layout layer fill style problem

Status
Not open for further replies.
G

goatmxj666

Member level 3
Member level 3
Joined
Mar 5, 2023
Messages
55
Helped
0
Reputation
0
Reaction score
1
Trophy points
8
Activity points
540
Hello,

when I check (CIW window -> Tools -> Display Resource manager -> edit) SDPW layer's 'Fill Style', it is set to 'outlineStipple'.

But, when I do layout, SDPW layer is set to 'blank'

Is it wrong that it looks different in the layout even after setting it?

I am wondering about how to reflect the settings in the 'Display Resource Editor' in the layout,

and what problems can actually occur when it is not reflected.

Thanks.

1679664224256.png

(my settings)


1679664249993.png

(in layout)
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top