Cadence encounter via connection issue?????

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crazzy_analog

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Hi,

I need a little help to define LEF technology file.
How can i distinguish several via define in the LEF file.
For example, i have DEFAULT via1 and also i have another via call fvia1 (fat via) which i can use for wide metal connection.
Currently i have always use DEFAULT via every connection that include power and ground connection.
Do i need to define different way to two different via that i have above?

Thanks
 

I usually do so. It is not able generate different vias even if there are defined VIA GENERATE rules in LEF file.
Funny thing is it's able generate matrix of vias to power routing but not use double via for signal wires.
 

jirika said:
I usually do so. It is not able generate different vias even if there are defined VIA GENERATE rules in LEF file.
Funny thing is it's able generate matrix of vias to power routing but not use double via for signal wires.
Click to expand...

Thank you for reply and as you said that even if we have different design rule such as array via rule is different from regular via rule, i can not define the different rule?
 

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