Cadence DRC Design Error

[gerberw1]

Have an interesting Cadence error, after running DRC, "Has Multiple Stamped Connections". I know what it is, something to do parasitic resistance calculations on more than one substrate connection. Any idea where I can find the info to fix the problem, already tried Cadence help and Google. Have you seen this error? This circuit is an inverter circuit from the Cadence library so the error must be fixable.

THANKS!

 

[rojyar_2020]

I have this problem too
It occur even i put only 1 transistor in LSW window!!