I tried to setup corner simulation in Virtuoso Analog Design Environment/Tools/Corners. By adding variable, I set VDD to be varied according to different corners. By adding corners, I set the required corners, such as typical, ff and ss. However, after i run simulation and plot the VDD from the schematic, it's the same in all corners. May I know anything missing in my setup? Thanks.
I didn't use global VDD. I did the same way as you. Do you mean to change the value of Vdc source for each corner, or the simulation will auto-change it according to each corner? Thanks.
if you to test the vdd corners so badly why don't you change it by your hand for example if the supply
spec 1.6-2.2 but vdd=2.2 and then choose the section you want from the model files ff,tt,ss and run the simulation(this depend on the kit you working on try to find it is manual)